[Intel-gfx] [PATCH v4 00/21] Add support for GuC-based SLPC

[tom.orourke at intel.com]

From: Tom O'Rourke <Tom.O'Rourke at intel.com>

SLPC (Single Loop Power Controller) is a replacement for
some host-based power management features.  The SLPC
implemenation runs in firmware on GuC.

This series has been tested with SKL guc firmware
version 6.1.

The graphics power management features in SLPC in those
versions are called GTPERF, BALANCER, and DCC.

GTPERF is a combination of DFPS (Dynamic FPS) and Turbo.
DFPS adjusts requested graphics frequency to maintain
target framerate.  Turbo adjusts requested graphics
frequency to maintain target GT busyness; this includes
an adaptive boost turbo method.

BALANCER adjusts balance between power budgets for IA
and GT in power limited scenarios.  BALANCER is only
active when all display pipes are in "game" mode.

DCC (Duty Cycle Control) adjusts requested graphics
frequency and stalls guc-scheduler to maintain actual
graphics frequency in efficient range.

The v3 series can be found in the archive at
"[Intel-gfx] [PATCH v3 00/25] Add support for GuC-based SLPC"
https://lists.freedesktop.org/archives/intel-gfx/2016-April/091771.html

This v4 series incorporates feedback from internal code 
reviews for Android and Yocto projects.  This series also 
drops the Broxton patches; the Broxton firmware has not 
been published yet.  Broxton support can be added later 
when the Broxton firmware is available. 

Also, the "DO NOT MERGE" patches to enable SLPC and guc 
submission by default have been dropped.  These can be 
added later after SLPC has been shown to outperform 
host-based power management; this may require a newer 
version of the GuC firmware.

With SLPC disabled by default, this series should be 
safe to merge now. 

VIZ-6773, VIZ-6889

Sagar Arun Kamble (4):
  drm/i915/slpc: Add Display mode event related data structures
  drm/i915/slpc: Notification of Display mode change
  drm/i915/slpc: Notification of Refresh Rate change
  drm/i915/slpc: Fail intel_runtime_suspend if SLPC or RPS not active

Tom O'Rourke (17):
  drm/i915/slpc: Expose guc functions for use with SLPC
  drm/i915/slpc: Add has_slpc capability flag
  drm/i915/slpc: Add slpc_version_check
  drm/i915/slpc: Add enable_slpc module parameter
  drm/i915/slpc: Use intel_slpc_* functions if supported
  drm/i915/slpc: Enable SLPC in guc if supported
  drm/i915/slpc: If using SLPC, do not set frequency
  drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
  drm/i915/slpc: Setup rps frequency values during SLPC init
  drm/i915/slpc: Update current requested frequency
  drm/i915/slpc: Send reset event
  drm/i915/slpc: Send shutdown event
  drm/i915/slpc: Add slpc_status enum values
  drm/i915/slpc: Add parameter unset/set/get functions
  drm/i915/slpc: Add slpc support for max/min freq
  drm/i915/slpc: Add enable/disable debugfs for slpc
  drm/i915/slpc: Add i915_slpc_info to debugfs

 drivers/gpu/drm/i915/Makefile              |   5 +-
 drivers/gpu/drm/i915/i915_debugfs.c        | 456 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c            |   4 +-
 drivers/gpu/drm/i915/i915_drv.h            |   7 +
 drivers/gpu/drm/i915/i915_guc_submission.c |   6 +-
 drivers/gpu/drm/i915/i915_params.c         |   6 +
 drivers/gpu/drm/i915/i915_params.h         |   1 +
 drivers/gpu/drm/i915/i915_reg.h            |   1 +
 drivers/gpu/drm/i915/i915_sysfs.c          |  21 ++
 drivers/gpu/drm/i915/intel_display.c       |   2 +
 drivers/gpu/drm/i915/intel_dp.c            |   2 +
 drivers/gpu/drm/i915/intel_drv.h           |  11 +
 drivers/gpu/drm/i915/intel_guc.h           |  13 +
 drivers/gpu/drm/i915/intel_guc_loader.c    |  36 ++
 drivers/gpu/drm/i915/intel_pm.c            |  42 ++-
 drivers/gpu/drm/i915/intel_slpc.c          | 516 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_slpc.h          | 217 ++++++++++++
 17 files changed, 1329 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

-- 
1.9.1