[Intel-gfx] [PATCH] drm/i915: Protect gen7 irq_seqno_barrier with uncore lock

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> [ text/plain ]
> Faced with sporadic machine hangs on gen7, that mimic the issue of
> concurrent writes to the same cacheline and seem to start with
> commit 9b9ed309 (drm/i915: Remove forcewake dance from seqno/irq
> barrier on legacy gen6+), let us restore the spinlock around the mmio
> read.
>
> Fixes: 9b9ed3093613288247a27a55a6dd07f1222150f1
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>

After 23 hours and 2078 GpuTest07 runs the box is healthy so:

Tested-by: Mika Kuoppala <mika.kuoppala at intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 66f69cdd1d36..ad5bd3808d8b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1590,7 +1590,10 @@ gen6_seqno_barrier(struct intel_engine_cs *engine)
>  	 * interrupt (with the same net latency).
>  	 */
>  	struct drm_i915_private *dev_priv = engine->dev->dev_private;
> +
> +	spin_lock_irq(&dev_priv->uncore.lock);
>  	POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
> +	spin_unlock_irq(&dev_priv->uncore.lock);

I was thinking that comment would be needed for the casual reader.
But perhaps the blatant unorthodoxity is big enough warning sign
to tread carefully here.

-Mika


>  }
>  
>  static u32
> -- 
> 2.8.1