[Intel-gfx] [PATCH i-g-t 3/3] tools/intel_reg: Dump DP_BUFTRANS registers on ILK-IVB

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 lib/intel_reg.h          |  2 ++
 tools/intel_reg_decode.c | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 0ffa803dab8d..3a28c08c3595 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3099,6 +3099,8 @@ typedef enum {
 #define TRANSC_DP_LINK_M2	0xe2048
 #define TRANSC_DP_LINK_N2	0xe204c
 
+#define DP_BUFTRANS(x)		(0xe4f00 + 4 * (x))
+
 #define TRANSACONF		0xf0008
 #define TRANSBCONF		0xf1008
 #define TRANSCCONF		0xf2008
diff --git a/tools/intel_reg_decode.c b/tools/intel_reg_decode.c
index 2d79290a4b58..98415fe8ae31 100644
--- a/tools/intel_reg_decode.c
+++ b/tools/intel_reg_decode.c
@@ -1540,6 +1540,26 @@ DEBUGSTRING(ironlake_debug_hdmi)
 		 enable, disp_pipe + 'A', bpc, encoding, mode, audio, vsync, hsync, detect);
 }
 
+DEBUGSTRING(ironlake_debug_dp_buftrans)
+{
+	static const char * const reg_names[] = {
+		"400mV, 0.0dB",
+		"400mV, 3.5dB",
+		"400mV, 6.0dB",
+		"400mV, 9.5dB",
+		"600mV, 0.0dB",
+		"600mV, 3.5dB",
+		"600mV, 6.0dB",
+		"800mV, 0.0dB",
+		"800mV, 3.5dB",
+		"1200mV, 0.0dB",
+	};
+	int idx = (reg - DP_BUFTRANS(0)) / 4;
+
+	return z_snprintf(result, len, "%s: OE=%3d, pre-emphasis=%2d, P current drive=%2d, N current drive=%2d",
+			  reg_names[idx], (val >> 19) & 0x1ff, (val >> 12) & 0x1f, (val >> 6) & 0xf, val & 0xf);
+}
+
 DEBUGSTRING(snb_debug_dpll_sel)
 {
 	const char *transa, *transb;
@@ -2304,6 +2324,18 @@ static const struct reg_debug ironlake_debug_regs[] = {
 	DEFINEREG(PCH_DP_B),
 	DEFINEREG(PCH_DP_C),
 	DEFINEREG(PCH_DP_D),
+
+	DEFINEREG2(DP_BUFTRANS(0), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(1), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(2), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(3), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(4), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(5), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(6), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(7), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(8), ironlake_debug_dp_buftrans),
+	DEFINEREG2(DP_BUFTRANS(9), ironlake_debug_dp_buftrans),
+
 	DEFINEREG2(TRANS_DP_CTL_A, snb_debug_trans_dp_ctl),
 	DEFINEREG2(TRANS_DP_CTL_B, snb_debug_trans_dp_ctl),
 	DEFINEREG2(TRANS_DP_CTL_C, snb_debug_trans_dp_ctl),
-- 
2.7.4