[Intel-gfx] [PATCH 05/33] drm/i915: Reduce amount of duplicate buffer information captured on error

[Chris Wilson]

On Wed, Aug 10, 2016 at 11:07:46AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-08-10 at 08:15 +0100, Chris Wilson wrote:
> > On Wed, Aug 10, 2016 at 10:04:16AM +0300, Joonas Lahtinen wrote:
> > > 
> > > On su, 2016-08-07 at 15:45 +0100, Chris Wilson wrote:
> > > > 
> > > > -	if (i) {
> > > > +	active_bo = NULL;
> > > Could be initialized at declaration for better readability.
> > No. I disagree strongly. I dislike having to go back to the beginning of
> > the block to check to see if was initialised before the if-chain that
> > otherwise sets the value.
> 
> GCC has captured such an uninitialized variable scenario for quite a
> while. Just increases noise.

Imo batching the use together as in this patch improves the signal as
the reader can see everything in a single block.

> > > >  /* Capture all registers which don't fit into another category. */
> > > >  static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
> > > >  				   struct drm_i915_error_state *error)
> > > > @@ -1436,10 +1402,12 @@ void i915_capture_error_state(struct drm_i915_private *dev_priv,
> > > >  
> > > >  	i915_capture_gen_state(dev_priv, error);
> > > >  	i915_capture_reg_state(dev_priv, error);
> > > > -	i915_gem_capture_buffers(dev_priv, error);
> > > >  	i915_gem_record_fences(dev_priv, error);
> > > >  	i915_gem_record_rings(dev_priv, error);
> > > >  
> > > > +	i915_capture_active_buffers(dev_priv, error);
> > > > +	i915_capture_pinned_buffers(dev_priv, error);
> > > > +
> > > Any specific reason for reordering here?
> > Different varieties of state capture, trying to use whitespace for
> > grouping.
> 
> Maybe keep it at current place and add whitespace before and after,
> making it three blocks?

gen_state, reg_state, record_fences are register state.

record_rings is a mix of register and associated buffers.

capture_*_buffers are the list of user buffers in the GTTs.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre