[Intel-gfx] [PATCH v3 12/21] drm/i915: Move HAS_GMBUS_IRQ definition to platform definition

[Rodrigo Vivi]

On Tue, Aug 09, 2016 at 11:45:18AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 


Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> Signed-off-by: Carlos Santa <carlos.santa at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 6 ++++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c4621ae..729a91b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -777,6 +777,7 @@ struct intel_csr {
>  	func(has_rc6) sep \
>  	func(has_rc6p) sep \
>  	func(has_dp_mst) sep \
> +	func(has_gmbus_irq) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2753,7 +2754,7 @@ struct drm_i915_cmd_table {
>   * interrupt source and so prevents the other device from working properly.
>   */
>  #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
> -#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
> +#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
>  
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 8a50e45..59c958a4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -181,6 +181,7 @@ static const struct intel_device_info intel_pineview_info = {
>  #define GEN5_FEATURES \
>  	.gen = 5, .num_pipes = 2, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
> +	.has_gmbus_irq = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
> @@ -202,6 +203,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  	.has_llc = 1, \
>  	.has_rc6 = 1, \
>  	.has_rc6p = 1, \
> +	.has_gmbus_irq = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	CURSOR_OFFSETS
>  
> @@ -222,6 +224,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.has_llc = 1, \
>  	.has_rc6 = 1, \
>  	.has_rc6p = 1, \
> +	.has_gmbus_irq = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
>  	IVB_CURSOR_OFFSETS
>  
> @@ -247,6 +250,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>  	.has_psr = 1, \
>  	.has_runtime_pm = 1, \
>  	.has_rc6 = 1, \
> +	.has_gmbus_irq = 1, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -300,6 +304,7 @@ static const struct intel_device_info intel_cherryview_info = {
>  	.has_runtime_pm = 1,
>  	.has_resource_streamer = 1,
>  	.has_rc6 = 1,
> +	.has_gmbus_irq = 1,
>  	.display_mmio_offset = VLV_DISPLAY_BASE,
>  	GEN_CHV_PIPEOFFSETS,
>  	CURSOR_OFFSETS,
> @@ -336,6 +341,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_resource_streamer = 1,
>  	.has_rc6 = 1,
>  	.has_dp_mst = 1,
> +	.has_gmbus_irq = 1,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx