[Intel-gfx] [PATCH] drm/i915: Mark up the GTT flush following WC writes as ORIGIN_CPU

[Zanoni, Paulo R]

Em Qua, 2016-08-17 às 19:20 +0100, Chris Wilson escreveu:
> Similarly to invalidating beforehand, if the object is mmapped via
> I915_MMAP_WC we cannot track writes through the I915_GEM_DOMAIN_GTT.
> At
> the conclusion of the write, i915_gem_object_flush_gtt_writes() we
> also
> need to treat the origin carefully in case it may have been
> untracked.
> 
> See also commit aeecc9696aa0 ("drm/i915: use ORIGIN_CPU for
> frontbuffer
> invalidation on WC mmaps").

This patch doesn't apply cleanly to drm-intel-nightly. I reviewed it
based on the current state of my tree, and it makes sense to me, so
unless your tree as super significant changes in this area:

Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index 161efa96aeda..d07ff0138deb 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3105,7 +3105,7 @@ i915_gem_object_flush_gtt_write_domain(struct
> drm_i915_gem_object *obj)
>  	if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv))
>  		POSTING_READ(RING_ACTHD(dev_priv-
> >engine[RCS].mmio_base));
>  
> -	intel_fb_obj_flush(obj, false, ORIGIN_GTT);
> +	intel_fb_obj_flush(obj, false, write_origin(obj,
> I915_GEM_DOMAIN_GTT));
>  
>  	obj->base.write_domain = 0;
>  	trace_i915_gem_object_change_domain(obj,