[Intel-gfx] [PATCH 2/2] drm/i915/fbc: Allow on unfenced surfaces, for recent gen

[Zanoni, Paulo R]

Em Qui, 2016-08-18 às 09:21 +0100, Chris Wilson escreveu:
> Only fbc1 is tied to using a fence. Later iterations of fbc are more
> flexible and allow operation on unfenced frontbuffers.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel.vetter at intel.com>
> Cc: "Zanoni, Paulo R" <paulo.r.zanoni at intel.com>

Hi

I see this patch was applied. Now, on my Skylake machine, if I boot
with i915.enable_fbc=1 I'll get FIFO underruns under fbcon. Just
booting already gives me a FIFO underrun message, and then if I "sudo
systemctl stop lightdm" I'll get a constantly-blinking screen.

Of course, applying the patch that disables FBC after a FIFO underrun
will help stopping the ever-blinking fbcon, but I think we should try
to avoid the underruns in the places we know we can, and leave the
"disable FBC on FIFO underruns" just for the cases we're not expecting.

Also, please remember that I mentioned there are FBC workarounds for
untiled that we still don't implement. IMHO this argument alone should
have prevented this patch from being merged...

Based on that, can we please revert this patch? I'm afraid some people
would consider these underruns as blockers to enabling FBC, so it's
probably better to enable FBC only on X tiled for now, and leave this
for when we know how to prevent the underrun.

Thanks,
Paulo

> ---
>  drivers/gpu/drm/i915/intel_fbc.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 57e1ca624d73..9534f90c6551 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -789,8 +789,10 @@ static bool intel_fbc_can_activate(struct
> intel_crtc *crtc)
>  	 */
>  	if (cache->fb.tiling_mode != I915_TILING_X ||
>  	    cache->fb.fence_reg == I915_FENCE_REG_NONE) {
> -		fbc->no_fbc_reason = "framebuffer not tiled or
> fenced";
> -		return false;
> +		if (INTEL_GEN(dev_priv) < 5) {
> +			fbc->no_fbc_reason = "framebuffer not tiled
> or fenced";
> +			return false;
> +		}
>  	}
>  	if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
>  	    cache->plane.rotation != DRM_ROTATE_0) {