[Intel-gfx] [CI] Revert "drm/i915/fbc: Allow on unfenced surfaces, for recent gen"

[Zanoni, Paulo R]

Em Qua, 2016-08-24 às 19:00 +0100, Chris Wilson escreveu:
> This reverts commit 8678fdaf396c ("drm/i915/fbc: Allow on unfenced
> surfaces,
> for recent gen") as Skylake has issues with unfenced FBC tracking
> (and
> yes Skylake doesn't even enable FBC yet)

But it used to work if you had i915.enable_fbc=1 after your latest
fixes :)

> . Paulo would like to do a full
> review of all existing workarounds to see if any more are missing
> prior
> to allowing FBC on unfenced surfaces

We are missing at least one workaround for this, and it's described in
the FBC_CTL page of BSpec for SKL, bit 31 description: we need to
calculate the compressed buffer stride and program it to a register.

I didin't say I would do the review of all existing workarounds, just
that someone needs to do this before enabling FBC on non-X-tiled
buffers since I recall skipping the implementation of workarounds that
didn't apply to X-tiling. Maybe the one I mentioned was the only one,
maybe not.

Also, our test suite only tests X tiling, and the
kms_frontbuffer_tracking/fbc-tilingchange will need to be updated.

> . In the meantime lets hope that all
> framebuffers are idle and naturally fit within the mappable aperture.

What exactly do you mean with the sentence above? Is there some other
bug you spotted? Please share the information.

> 
> Requested-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Fixes: 8678fdaf396c ("drm/i915/fbc: Allow on unfenced surfaces...");
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_fbc.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index bf8b22ad9aed..faa67624e1ed 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -799,10 +799,8 @@ static bool intel_fbc_can_activate(struct
> intel_crtc *crtc)
>  	 */
>  	if (cache->fb.tiling_mode != I915_TILING_X ||
>  	    cache->fb.fence_reg == I915_FENCE_REG_NONE) {
> -		if (INTEL_GEN(dev_priv) < 5) {
> -			fbc->no_fbc_reason = "framebuffer not tiled
> or fenced";
> -			return false;
> -		}
> +		fbc->no_fbc_reason = "framebuffer not tiled or
> fenced";
> +		return false;
>  	}
>  	if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
>  	    cache->plane.rotation != DRM_ROTATE_0) {