[Intel-gfx] [PATCH v3] drm/i915: replace platform flags with a platform enum
Jani Nikula
jani.nikula at intel.com
Thu Dec 1 12:49:55 UTC 2016
The platform flags in device info are (mostly) mutually
exclusive. Replace the flags with an enum. Add the platform enum also
for platforms that previously didn't have a flag, and give them codename
logging in dmesg.
Pineview remains an exception, the platform being G33 for that.
v2: Sort enum by gen and date
v3: rebase on geminilake enabling
Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 80 +++++++++++++++++++-------------
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_pci.c | 57 +++++++++++++----------
drivers/gpu/drm/i915/intel_device_info.c | 41 +++++++++++++++-
5 files changed, 122 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2434130087be..15fb97dd9ed3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -77,6 +77,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
const struct intel_device_info *info = INTEL_INFO(dev_priv);
seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
+ seq_printf(m, "platform: %s\n", intel_platform_name(info->platform));
seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 34f2b0da6a81..7fd0279af635 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -686,25 +686,8 @@ struct intel_csr {
};
#define DEV_INFO_FOR_EACH_FLAG(func) \
- /* Keep is_* in chronological order */ \
func(is_mobile); \
- func(is_i85x); \
- func(is_i915g); \
- func(is_i945gm); \
- func(is_g33); \
- func(is_g4x); \
func(is_pineview); \
- func(is_broadwater); \
- func(is_crestline); \
- func(is_ivybridge); \
- func(is_valleyview); \
- func(is_cherryview); \
- func(is_haswell); \
- func(is_broadwell); \
- func(is_skylake); \
- func(is_broxton); \
- func(is_geminilake); \
- func(is_kabylake); \
func(is_lp); \
func(is_alpha_support); \
/* Keep has_* in alphabetical order */ \
@@ -755,6 +738,35 @@ static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}
+/* Keep in gen based order, and chronological order within a gen */
+enum intel_platform {
+ INTEL_PLATFORM_UNINITIALIZED = 0,
+ INTEL_I830,
+ INTEL_I845G,
+ INTEL_I85X,
+ INTEL_I865G,
+ INTEL_I915G,
+ INTEL_I915GM,
+ INTEL_I945G,
+ INTEL_I945GM,
+ INTEL_G33,
+ INTEL_PINEVIEW,
+ INTEL_BROADWATER,
+ INTEL_CRESTLINE,
+ INTEL_G4X,
+ INTEL_IRONLAKE,
+ INTEL_SANDYBRIDGE,
+ INTEL_IVYBRIDGE,
+ INTEL_VALLEYVIEW,
+ INTEL_HASWELL,
+ INTEL_BROADWELL,
+ INTEL_CHERRYVIEW,
+ INTEL_SKYLAKE,
+ INTEL_BROXTON,
+ INTEL_KABYLAKE,
+ INTEL_GEMINILAKE,
+};
+
struct intel_device_info {
u32 display_mmio_offset;
u16 device_id;
@@ -762,6 +774,7 @@ struct intel_device_info {
u8 num_sprites[I915_MAX_PIPES];
u8 gen;
u16 gen_mask;
+ enum intel_platform platform;
u8 ring_mask; /* Rings supported by the HW */
u8 num_rings;
#define DEFINE_FLAG(name) u8 name:1
@@ -2499,33 +2512,33 @@ intel_info(const struct drm_i915_private *dev_priv)
#define IS_I830(dev_priv) (INTEL_DEVID(dev_priv) == 0x3577)
#define IS_845G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2562)
-#define IS_I85X(dev_priv) ((dev_priv)->info.is_i85x)
+#define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X)
#define IS_I865G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2572)
-#define IS_I915G(dev_priv) ((dev_priv)->info.is_i915g)
+#define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G)
#define IS_I915GM(dev_priv) (INTEL_DEVID(dev_priv) == 0x2592)
#define IS_I945G(dev_priv) (INTEL_DEVID(dev_priv) == 0x2772)
-#define IS_I945GM(dev_priv) ((dev_priv)->info.is_i945gm)
-#define IS_BROADWATER(dev_priv) ((dev_priv)->info.is_broadwater)
-#define IS_CRESTLINE(dev_priv) ((dev_priv)->info.is_crestline)
+#define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM)
+#define IS_BROADWATER(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWATER)
+#define IS_CRESTLINE(dev_priv) ((dev_priv)->info.platform == INTEL_CRESTLINE)
#define IS_GM45(dev_priv) (INTEL_DEVID(dev_priv) == 0x2A42)
-#define IS_G4X(dev_priv) ((dev_priv)->info.is_g4x)
+#define IS_G4X(dev_priv) ((dev_priv)->info.platform == INTEL_G4X)
#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
#define IS_PINEVIEW(dev_priv) ((dev_priv)->info.is_pineview)
-#define IS_G33(dev_priv) ((dev_priv)->info.is_g33)
+#define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33)
#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
-#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.is_ivybridge)
+#define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)
#define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \
INTEL_DEVID(dev_priv) == 0x0152 || \
INTEL_DEVID(dev_priv) == 0x015a)
-#define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.is_valleyview)
-#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.is_cherryview)
-#define IS_HASWELL(dev_priv) ((dev_priv)->info.is_haswell)
-#define IS_BROADWELL(dev_priv) ((dev_priv)->info.is_broadwell)
-#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.is_skylake)
-#define IS_BROXTON(dev_priv) ((dev_priv)->info.is_broxton)
-#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.is_geminilake)
-#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.is_kabylake)
+#define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW)
+#define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW)
+#define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL)
+#define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL)
+#define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE)
+#define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON)
+#define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE)
+#define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE)
#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -3560,6 +3573,7 @@ mkwrite_device_info(struct drm_i915_private *dev_priv)
return (struct intel_device_info *)&dev_priv->info;
}
+const char *intel_platform_name(enum intel_platform platform);
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 82458ea60150..ee70cba7cf7b 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -547,6 +547,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
}
err_printf(m, "Reset count: %u\n", error->reset_count);
err_printf(m, "Suspend count: %u\n", error->suspend_count);
+ err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
err_printf(m, "PCI Subsystem: %04x:%04x\n",
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 389a33090707..e52279c6ea6d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -65,17 +65,19 @@
static const struct intel_device_info intel_i830_info = {
GEN2_FEATURES,
+ .platform = INTEL_I830,
.is_mobile = 1, .cursor_needs_physical = 1,
.num_pipes = 2, /* legal, last one wins */
};
static const struct intel_device_info intel_845g_info = {
GEN2_FEATURES,
+ .platform = INTEL_I845G,
};
static const struct intel_device_info intel_i85x_info = {
GEN2_FEATURES,
- .is_i85x = 1, .is_mobile = 1,
+ .platform = INTEL_I85X, .is_mobile = 1,
.num_pipes = 2, /* legal, last one wins */
.cursor_needs_physical = 1,
.has_fbc = 1,
@@ -83,6 +85,7 @@ static const struct intel_device_info intel_i85x_info = {
static const struct intel_device_info intel_i865g_info = {
GEN2_FEATURES,
+ .platform = INTEL_I865G,
};
#define GEN3_FEATURES \
@@ -94,12 +97,13 @@ static const struct intel_device_info intel_i865g_info = {
static const struct intel_device_info intel_i915g_info = {
GEN3_FEATURES,
- .is_i915g = 1, .cursor_needs_physical = 1,
+ .platform = INTEL_I915G, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.hws_needs_physical = 1,
};
static const struct intel_device_info intel_i915gm_info = {
GEN3_FEATURES,
+ .platform = INTEL_I915GM,
.is_mobile = 1,
.cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
@@ -109,13 +113,14 @@ static const struct intel_device_info intel_i915gm_info = {
};
static const struct intel_device_info intel_i945g_info = {
GEN3_FEATURES,
+ .platform = INTEL_I945G,
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.hws_needs_physical = 1,
};
static const struct intel_device_info intel_i945gm_info = {
GEN3_FEATURES,
- .is_i945gm = 1, .is_mobile = 1,
+ .platform = INTEL_I945GM, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
@@ -133,14 +138,14 @@ static const struct intel_device_info intel_i945gm_info = {
static const struct intel_device_info intel_i965g_info = {
GEN4_FEATURES,
- .is_broadwater = 1,
+ .platform = INTEL_BROADWATER,
.has_overlay = 1,
.hws_needs_physical = 1,
};
static const struct intel_device_info intel_i965gm_info = {
GEN4_FEATURES,
- .is_crestline = 1,
+ .platform = INTEL_CRESTLINE,
.is_mobile = 1, .has_fbc = 1,
.has_overlay = 1,
.supports_tv = 1,
@@ -149,21 +154,21 @@ static const struct intel_device_info intel_i965gm_info = {
static const struct intel_device_info intel_g33_info = {
GEN3_FEATURES,
- .is_g33 = 1,
+ .platform = INTEL_G33,
.has_hotplug = 1,
.has_overlay = 1,
};
static const struct intel_device_info intel_g45_info = {
GEN4_FEATURES,
- .is_g4x = 1,
+ .platform = INTEL_G4X,
.has_pipe_cxsr = 1,
.ring_mask = RENDER_RING | BSD_RING,
};
static const struct intel_device_info intel_gm45_info = {
GEN4_FEATURES,
- .is_g4x = 1,
+ .platform = INTEL_G4X,
.is_mobile = 1, .has_fbc = 1,
.has_pipe_cxsr = 1,
.supports_tv = 1,
@@ -172,7 +177,7 @@ static const struct intel_device_info intel_gm45_info = {
static const struct intel_device_info intel_pineview_info = {
GEN3_FEATURES,
- .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
+ .platform = INTEL_G33, .is_pineview = 1, .is_mobile = 1,
.has_hotplug = 1,
.has_overlay = 1,
};
@@ -187,10 +192,12 @@ static const struct intel_device_info intel_pineview_info = {
static const struct intel_device_info intel_ironlake_d_info = {
GEN5_FEATURES,
+ .platform = INTEL_IRONLAKE,
};
static const struct intel_device_info intel_ironlake_m_info = {
GEN5_FEATURES,
+ .platform = INTEL_IRONLAKE,
.is_mobile = 1,
};
@@ -209,10 +216,12 @@ static const struct intel_device_info intel_ironlake_m_info = {
static const struct intel_device_info intel_sandybridge_d_info = {
GEN6_FEATURES,
+ .platform = INTEL_SANDYBRIDGE,
};
static const struct intel_device_info intel_sandybridge_m_info = {
GEN6_FEATURES,
+ .platform = INTEL_SANDYBRIDGE,
.is_mobile = 1,
};
@@ -231,20 +240,20 @@ static const struct intel_device_info intel_sandybridge_m_info = {
static const struct intel_device_info intel_ivybridge_d_info = {
GEN7_FEATURES,
- .is_ivybridge = 1,
+ .platform = INTEL_IVYBRIDGE,
.has_l3_dpf = 1,
};
static const struct intel_device_info intel_ivybridge_m_info = {
GEN7_FEATURES,
- .is_ivybridge = 1,
+ .platform = INTEL_IVYBRIDGE,
.is_mobile = 1,
.has_l3_dpf = 1,
};
static const struct intel_device_info intel_ivybridge_q_info = {
GEN7_FEATURES,
- .is_ivybridge = 1,
+ .platform = INTEL_IVYBRIDGE,
.num_pipes = 0, /* legal, last one wins */
.has_l3_dpf = 1,
};
@@ -265,7 +274,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
static const struct intel_device_info intel_valleyview_info = {
VLV_FEATURES,
- .is_valleyview = 1,
+ .platform = INTEL_VALLEYVIEW,
};
#define HSW_FEATURES \
@@ -281,7 +290,7 @@ static const struct intel_device_info intel_valleyview_info = {
static const struct intel_device_info intel_haswell_info = {
HSW_FEATURES,
- .is_haswell = 1,
+ .platform = INTEL_HASWELL,
.has_l3_dpf = 1,
};
@@ -294,13 +303,13 @@ static const struct intel_device_info intel_haswell_info = {
static const struct intel_device_info intel_broadwell_info = {
BDW_FEATURES,
.gen = 8,
- .is_broadwell = 1,
+ .platform = INTEL_BROADWELL,
};
static const struct intel_device_info intel_broadwell_gt3_info = {
BDW_FEATURES,
.gen = 8,
- .is_broadwell = 1,
+ .platform = INTEL_BROADWELL,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
};
@@ -308,7 +317,7 @@ static const struct intel_device_info intel_cherryview_info = {
.gen = 8, .num_pipes = 3,
.has_hotplug = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
- .is_cherryview = 1,
+ .platform = INTEL_CHERRYVIEW,
.has_64bit_reloc = 1,
.has_psr = 1,
.has_runtime_pm = 1,
@@ -326,7 +335,7 @@ static const struct intel_device_info intel_cherryview_info = {
static const struct intel_device_info intel_skylake_info = {
BDW_FEATURES,
- .is_skylake = 1,
+ .platform = INTEL_SKYLAKE,
.gen = 9,
.has_csr = 1,
.has_guc = 1,
@@ -335,7 +344,7 @@ static const struct intel_device_info intel_skylake_info = {
static const struct intel_device_info intel_skylake_gt3_info = {
BDW_FEATURES,
- .is_skylake = 1,
+ .platform = INTEL_SKYLAKE,
.gen = 9,
.has_csr = 1,
.has_guc = 1,
@@ -369,21 +378,21 @@ static const struct intel_device_info intel_skylake_gt3_info = {
BDW_COLORS
static const struct intel_device_info intel_broxton_info = {
- .is_broxton = 1,
GEN9_LP_FEATURES,
+ .platform = INTEL_BROXTON,
.ddb_size = 512,
};
static const struct intel_device_info intel_geminilake_info = {
- .is_alpha_support = 1,
- .is_geminilake = 1,
GEN9_LP_FEATURES,
+ .platform = INTEL_GEMINILAKE,
+ .is_alpha_support = 1,
.ddb_size = 1024,
};
static const struct intel_device_info intel_kabylake_info = {
BDW_FEATURES,
- .is_kabylake = 1,
+ .platform = INTEL_KABYLAKE,
.gen = 9,
.has_csr = 1,
.has_guc = 1,
@@ -392,7 +401,7 @@ static const struct intel_device_info intel_kabylake_info = {
static const struct intel_device_info intel_kabylake_gt3_info = {
BDW_FEATURES,
- .is_kabylake = 1,
+ .platform = INTEL_KABYLAKE,
.gen = 9,
.has_csr = 1,
.has_guc = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 185e3bbc9ec9..eeda44839671 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -24,11 +24,50 @@
#include "i915_drv.h"
+#define PLATFORM_NAME(x) [INTEL_##x] = #x
+static const char * const platform_names[] = {
+ PLATFORM_NAME(I830),
+ PLATFORM_NAME(I845G),
+ PLATFORM_NAME(I85X),
+ PLATFORM_NAME(I865G),
+ PLATFORM_NAME(I915G),
+ PLATFORM_NAME(I915GM),
+ PLATFORM_NAME(I945G),
+ PLATFORM_NAME(I945GM),
+ PLATFORM_NAME(G33),
+ PLATFORM_NAME(PINEVIEW),
+ PLATFORM_NAME(BROADWATER),
+ PLATFORM_NAME(CRESTLINE),
+ PLATFORM_NAME(G4X),
+ PLATFORM_NAME(IRONLAKE),
+ PLATFORM_NAME(SANDYBRIDGE),
+ PLATFORM_NAME(IVYBRIDGE),
+ PLATFORM_NAME(VALLEYVIEW),
+ PLATFORM_NAME(HASWELL),
+ PLATFORM_NAME(BROADWELL),
+ PLATFORM_NAME(CHERRYVIEW),
+ PLATFORM_NAME(SKYLAKE),
+ PLATFORM_NAME(BROXTON),
+ PLATFORM_NAME(KABYLAKE),
+ PLATFORM_NAME(GEMINILAKE),
+};
+#undef PLATFORM_NAME
+
+const char *intel_platform_name(enum intel_platform platform)
+{
+ if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
+ platform_names[platform] == NULL))
+ return "<unknown>";
+
+ return platform_names[platform];
+}
+
void intel_device_info_dump(struct drm_i915_private *dev_priv)
{
const struct intel_device_info *info = &dev_priv->info;
- DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x",
+ DRM_DEBUG_DRIVER("i915 device info: platform=%s gen=%i pciid=0x%04x rev=0x%02x",
+ intel_platform_name(info->platform),
info->gen,
dev_priv->drm.pdev->device,
dev_priv->drm.pdev->revision);
--
2.1.4
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