[Intel-gfx] ✗ Fi.CI.BAT: warning for Geminilake enabling (rev9)
Ander Conselvan De Oliveira
conselvan2 at gmail.com
Fri Dec 2 14:47:14 UTC 2016
On Fri, 2016-12-02 at 09:17 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Geminilake enabling (rev9)
> URL : https://patchwork.freedesktop.org/series/15118/
> State : warning
>
> == Summary ==
>
> Series 15118v9 Geminilake enabling
> https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/9/mbox/
>
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b:
> pass -> DMESG-WARN (fi-ivb-3770)
*ERROR* EDID checksum is invalid, remainder is 157
https://bugs.freedesktop.org/show_bug.cgi?id=98228
Series pushed. Thanks for the reviews.
Ander
>
> fi-bdw-5557u total:245 pass:230 dwarn:0 dfail:0 fail:0 skip:15
> fi-bsw-n3050 total:245 pass:205 dwarn:0 dfail:0 fail:0 skip:40
> fi-bxt-t5700 total:245 pass:217 dwarn:0 dfail:0 fail:0 skip:28
> fi-byt-j1900 total:245 pass:217 dwarn:0 dfail:0 fail:0 skip:28
> fi-byt-n2820 total:245 pass:213 dwarn:0 dfail:0 fail:0 skip:32
> fi-hsw-4770 total:245 pass:225 dwarn:0 dfail:0 fail:0 skip:20
> fi-hsw-4770r total:245 pass:225 dwarn:0 dfail:0 fail:0 skip:20
> fi-ilk-650 total:245 pass:192 dwarn:0 dfail:0 fail:0 skip:53
> fi-ivb-3520m total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
> fi-ivb-3770 total:245 pass:222 dwarn:1 dfail:0 fail:0 skip:22
> fi-kbl-7500u total:245 pass:223 dwarn:0 dfail:0 fail:0 skip:22
> fi-skl-6260u total:245 pass:231 dwarn:0 dfail:0 fail:0 skip:14
> fi-skl-6700hq total:245 pass:224 dwarn:0 dfail:0 fail:0 skip:21
> fi-skl-6700k total:245 pass:223 dwarn:1 dfail:0 fail:0 skip:21
> fi-skl-6770hq total:245 pass:231 dwarn:0 dfail:0 fail:0 skip:14
> fi-snb-2520m total:245 pass:213 dwarn:0 dfail:0 fail:0 skip:32
> fi-snb-2600 total:245 pass:212 dwarn:0 dfail:0 fail:0 skip:33
>
> 58e999de1132de619056ee8fafccbbe7dfba3f4d drm-tip: 2016y-12m-02d-07h-55m-48s
> UTC integration manifest
> 1f087d4 drm/i915/glk: Configure number of sprite planes properly
> 0615d8a drm/i915/glk: Implement core display init/uninit sequence for
> geminilake
> 6ada4b4 drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
> 819a098 drm/i915/glk: Reuse broxton's cdclk code for GLK
> aa98396 drm/i915/glk: Update Port PLL enable sequence for Geminilkae
> da9e47e drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
> a59b507 drm/i915/glk: Implement Geminilake DDI init sequence
> 39714d8 drm/i915/glk: Add power wells for Geminilake
> 9b3c48c drm/i915/glk: Reuse broxton code for geminilake
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3168/
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