[Intel-gfx] ✗ Fi.CI.BAT: warning for Geminilake enabling (rev9)

[Saarinen, Jani]

> == Series Details ==
> 
> Series: Geminilake enabling (rev9)
> URL   : https://patchwork.freedesktop.org/series/15118/
> State : warning
> 
> == Summary ==
> 
> Series 15118v9 Geminilake enabling
> https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/9/mbox/
> 
> Test kms_pipe_crc_basic:
>         Subgroup read-crc-pipe-b:
>                 pass       -> DMESG-WARN (fi-ivb-3770)
*ERROR* EDID checksum is invalid, remainder is 157
=> 
https://bugs.freedesktop.org/show_bug.cgi?id=98228

> fi-ivb-3770      total:245  pass:222  dwarn:1   dfail:0   fail:0   skip:22
> 
> 58e999de1132de619056ee8fafccbbe7dfba3f4d drm-tip: 2016y-12m-02d-07h-
> 55m-48s UTC integration manifest
> 1f087d4 drm/i915/glk: Configure number of sprite planes properly 0615d8a
> drm/i915/glk: Implement core display init/uninit sequence for geminilake
> 6ada4b4 drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
> 819a098 drm/i915/glk: Reuse broxton's cdclk code for GLK
> aa98396 drm/i915/glk: Update Port PLL enable sequence for Geminilkae
> da9e47e drm/i915/glk: Set DCC delay range 2 in PLL enable sequence
> a59b507 drm/i915/glk: Implement Geminilake DDI init sequence
> 39714d8 drm/i915/glk: Add power wells for Geminilake 9b3c48c drm/i915/glk:
> Reuse broxton code for geminilake
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3168/


Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo