[Intel-gfx] [PATCH v2] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating

[Hans de Goede]

Hi,

On 05-12-16 19:52, Ville Syrjälä wrote:
> On Fri, Dec 02, 2016 at 03:29:04PM +0100, Hans de Goede wrote:
>> On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading
>> i915 at boot 1 out of every 3 boots, resulting in a non functional LCD.
>> Once the i915 driver has successfully loaded, the panel can be disabled /
>> enabled without hitting this issue.
>>
>> The getting stuck is caused by vlv_init_display_clock_gating() clearing
>> the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from
>> chv_pipe_power_well_ops.enable() on driver load, while a pipe is enabled
>> driving the DSI LCD by the BIOS.
>>
>> Clearing this bit while DSI is in use is a known issue and
>> intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it
>> as appropriate.
>>
>> This commit modifies vlv_init_display_clock_gating() to leave the
>> DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing the pipe getting stuck.
>>
>> BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=97330
>> Cc: stable at vger.kernel.org
>> Signed-off-by: Hans de Goede <hdegoede at redhat.com>
>> Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
>> ---
>> Changes in v2:
>> -Replace PIPE-A with "a pipe" or "the pipe" in the commit msg and comment
>
> Pushed to dinq with s/BugLink/Bugzilla/ and changelog moved into the
> commit message proper. Thanks for the patch.

Thank you, what about the other 2 bug-fix patches, the
assert/deassert swap one and the one setting the gpio_en bit for
cherryview ?

Regards,

Hans


>
>> ---
>>  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++++++-
>>  1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index 356c662..87b4af0 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -1039,7 +1039,18 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
>>
>>  static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>> +	u32 val;
>> +
>> +	/*
>> +	 * On driver load, a pipe may be active and driving a DSI display.
>> +	 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
>> +	 * (and never recovering) in this case. intel_dsi_post_disable() will
>> +	 * clear it when we turn off the display.
>> +	 */
>> +	val = I915_READ(DSPCLK_GATE_D);
>> +	val &= DPOUNIT_CLOCK_GATE_DISABLE;
>> +	val |= VRHUNIT_CLOCK_GATE_DISABLE;
>> +	I915_WRITE(DSPCLK_GATE_D, val);
>>
>>  	/*
>>  	 * Disable trickle feed and enable pnd deadline calculation
>> --
>> 2.9.3
>