[Intel-gfx] [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register

[Madhav Chauhan]

From: Deepak M <m.deepak at intel.com>

Signed-off-by: Deepak M <m.deepak at intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 90685d2..6bd68bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8658,6 +8658,21 @@ enum {
 #define _MIPIA_CTRL			(dev_priv->mipi_mmio_base + 0xb104)
 #define _MIPIC_CTRL			(dev_priv->mipi_mmio_base + 0xb904)
 #define MIPI_CTRL(port)			_MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
+#define  PHY_STATUS					(1 << 31) /* RO */
+#define  ULPS_NOT_ACTIVE				(1 << 30) /* RO */
+#define  MIPIIO_RESET					(1 << 28)
+#define  CLOCK_LANE_STOP_STATE				(1 << 27) /* RO */
+#define  DATA_LANE_STOP_STATE				(1 << 26) /* RO */
+#define  LP_WAKE					(1 << 22)
+#define  LP11_LOW_PWR_MODE				(1 << 21)
+#define  LP00_LOW_PWR_MODE				(1 << 20)
+#define  FIREWALL_ENABLE				(1 << 16)
+#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
+#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
+#define  DSC_ENABLE					(1 << 3)
+#define  RGB_FLIP					(1 << 2)
+#define  PWR_ACK					(1 << 1) /* RO */
+#define  MIPI_MODE					(1 << 0)
 #define  ESCAPE_CLOCK_DIVIDER_SHIFT			5 /* A only */
 #define  ESCAPE_CLOCK_DIVIDER_MASK			(3 << 5)
 #define  ESCAPE_CLOCK_DIVIDER_1				(0 << 5)
-- 
1.9.1