[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Introduce intel_cdclk_state (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Introduce intel_cdclk_state (rev2)
URL   : https://patchwork.freedesktop.org/series/16994/
State : success

== Summary ==

Series 16994v2 drm/i915: Introduce intel_cdclk_state
https://patchwork.freedesktop.org/api/1.0/series/16994/revisions/2/mbox/


fi-bdw-5557u     total:247  pass:233  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:247  pass:208  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:247  pass:225  dwarn:1   dfail:0   fail:0   skip:21 
fi-bxt-t5700     total:247  pass:220  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-j1900     total:247  pass:220  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-ilk-650       total:247  pass:195  dwarn:0   dfail:0   fail:0   skip:52 
fi-ivb-3520m     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:247  pass:227  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:247  pass:224  dwarn:3   dfail:0   fail:0   skip:20 
fi-skl-6770hq    total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:247  pass:215  dwarn:0   dfail:0   fail:0   skip:32 

cda2d70a4395323bcf064c81ee0f89d2de015544 drm-tip: 2016y-12m-19d-13h-00m-10s UTC integration manifest
d040558 drm/i915: Move ilk_pipe_pixel_rate() to intel_display.c
21b5832 drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cdclk() hook
2062a1a drm/i915: Nuke the VLV/CHV PFI programming power domain workaround
d038c72 drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()
78d684e drm/i915: Pass the cdclk state to the set_cdclk() functions
975f627 drm/i915: Pass dev_priv to remainder of the cdclk functions
7b6e5ff drm/i915: Track full cdclk state for the logical and actual cdclk frequencies
4ee69e5 drm/i915: Start moving the cdclk stuff into a distinct state structure
c09d12a drm/i915: Pass computed vco to bxt_set_cdclk()
a68c15c drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c
411c66a drm/i915: Clean up the .get_cdclk() assignment if ladder
970e62a drm/i915: s/get_display_clock_speed/get_cdclk/
0030606 drm/i915: Nuke intel_mode_max_pixclk()
5bd6e0f drm/i915: Store the pipe pixel rate in the crtc state

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3332/