[Intel-gfx] [PATCH] drm/i915/guc: Reserve the upper end of the Global GTT for the GuC

[Kamble, Sagar A]

On 12/22/2016 2:40 AM, Daniele Ceraolo Spurio wrote:
>
>
> On 21/12/16 06:11, Chris Wilson wrote:
>> The GuC would like to own the upper portion of the GTT for itself, so
>> exclude it from our drm_mm to prevent us using it.
>
> I had a quick chat with a GuC dev and he is pretty sure that GuC can't 
> reserve any GTT areas for itself (and that is why we do the allocation 
> for the buffers the GuC uses). However, it looks like the offsets 
> above 0xFEE00000 are reserved internally from the GuC point of view 
> for some private resources, similarly to what happens for the offsets 
> below GUC_WOPCM_TOP. This means that we should be able to actually use 
> those offsets from the host side, but we can't pass any object placed 
> there to GuC. The GuC FW will drop any operation on objects placed 
> above 0xFEE00000, which may be what caused the issues with 
> guc_submission (not sure of this since I haven't seen the report).
golden_context_lrca, reg_state, reg_state_buffer addresses in ADS that 
makes GuC load fail:
[    4.955330] [drm:i915_guc_submission_init [i915]]  fffe7000 8542c8 854b18

With this patch applied golden_context_lrca gets placed properly and GuC 
load succeeds.
[    4.953817] [drm:i915_guc_submission_init [i915]]  fede7000 8542c8 854b18
> The fix below might still be ok for us as reducing the GGTT size by a 
> small amount shouldn't be a big issue, but I'd prefer the comment and 
> the commit message to be updated.
>
> To also reply to Michal question, I was told that the region size is 
> fixed and not FW dependent.
>
> Thanks,
> Daniele
>
>>
>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
>> Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
>> Cc: Arkadiusz Hiler <arkadiusz.hiler at intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_gem_gtt.c   | 5 +++++
>>  drivers/gpu/drm/i915/intel_guc_fwif.h | 3 +++
>>  2 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
>> b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index 6af9311f72f5..96bc0e83286a 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -3176,6 +3176,11 @@ int i915_ggtt_probe_hw(struct drm_i915_private 
>> *dev_priv)
>>      if (ret)
>>          return ret;
>>
>> +    if (HAS_GUC_SCHED(dev_priv)) {
>> +        ggtt->base.total -= GUC_GGTT_RESERVED_TOP;
>> +        ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
>> +    }
>> +
>>      if ((ggtt->base.total - 1) >> 32) {
>>          DRM_ERROR("We never expected a Global GTT with more than 
>> 32bits"
>>                " of address space! Found %lldM!\n",
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index 3202b32b5638..3361d38ed859 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -23,6 +23,9 @@
>>  #ifndef _INTEL_GUC_FWIF_H
>>  #define _INTEL_GUC_FWIF_H
>>
>> +/* A small region at the top of the global GTT is reserved for use 
>> by the GuC */
>> +#define GUC_GGTT_RESERVED_TOP        0x1200000
>> +
>>  #define GFXCORE_FAMILY_GEN9        12
>>  #define GFXCORE_FAMILY_UNKNOWN        0x7fffffff
>>
>>
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