[Intel-gfx] [PATCH 12/14] drm/i915: Nuke the VLV/CHV PFI programming power domain workaround

[Ander Conselvan De Oliveira]

On Mon, 2016-12-19 at 19:28 +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> The hack to grab the pipe A power domain around VLV/CHV cdclk
> programming has surely outlived its usefulness. We should be
> hold sufficient power domains during any modeset, so let's just

hold/be holding?

Reviewed-by: Ander Conselvan de Oliveira <conselvan2 at gmail.com>

> nuke this hack.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 14 --------------
>  1 file changed, 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index fe7a9e3a4f29..bba077c4bd56 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1421,24 +1421,10 @@ static void vlv_modeset_commit_cdclk(struct
> drm_atomic_state *old_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(old_state->dev);
>  
> -	/*
> -	 * FIXME: We can end up here with all power domains off, yet
> -	 * with a CDCLK frequency other than the minimum. To account
> -	 * for this take the PIPE-A power domain, which covers the HW
> -	 * blocks needed for the following programming. This can be
> -	 * removed once it's guaranteed that we get here either with
> -	 * the minimum CDCLK set, or the required power domains
> -	 * enabled.
> -	 */
> -	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
> -
>  	if (IS_CHERRYVIEW(dev_priv))
>  		chv_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
>  	else
>  		vlv_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
> -
> -
> -	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
>  }
>  
>  static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)