[Intel-gfx] [PATCH V3] drm/i915/skl: SKL CDCLK change on modeset tracking VCO

[Ville Syrjälä]

On Tue, Feb 09, 2016 at 04:28:27PM -0800, clinton.a.taylor at intel.com wrote:
> From: Clint Taylor <clinton.a.taylor at intel.com>
> 
> Track VCO frequency of SKL instead of the boot CDCLK and allow modeset
> to set cdclk based on the max required pixel clock based on VCO
> selected.
> 
> The vco should be tracked at the atomic level and all CRTCs updated if
> the required vco is changed. At this time the eDP pll is configured
> inside the encoder which has no visibility into the atomic state. When
> eDP v1.4 panel that require the 8640 vco are available this may need
> to be investigated.
> 
> V1: initial version
> V2: add vco tracking in intel_dp_compute_config(), rename
> skl_boot_cdclk.
> V3: rebase, V2 feedback not possible as encoders are not aware of
> atomic.
> 
> Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
> Cc: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala at linux.intel.com>

BTW I think we might want a patch for stable that just removes the
max_cdclk setup for SKL/KBL (ie. just set max_cdclk=current cdclk).
We'd put that in first, then put in the final version of this patch,
and finally revert the first patch.

Without that, backporting any of the DP/HDMI max_dotclock check patches
to stable won't actually help SKL. Should we decide to backport those
that is.

-- 
Ville Syrjälä
Intel OTC