[Intel-gfx] [PATCH 16/21] drm/i915: Limit fb x offset due to fences

ville.syrjala at linux.intel.com ville.syrjala at linux.intel.com
Mon Feb 15 20:54:54 UTC 2016

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

If there's a fence on the object it will be aligned to the start
of the object, and hence CPU rendering to any fb that straddles
the fence edge will come out wrong due to lines wrapping at the
wrong place.

We have no API to manage fences on a sub-object level, so we can't
really fix this in any way. Additonally gen2/3 fences are rather
coarse grained so adjusting the offset migth not even be possible.

Avoid these problems by requiring the fb layout to agree with the
fence layout (if present).

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
 drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index de312af9b117..f805ec332393 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2643,6 +2643,22 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
 		intel_fb_offset_to_xy(&x, &y, fb, i);
+		 * The fence (if used) is aligned to the start of the object
+		 * so having the framebuffer wrap around across the edge of the
+		 * fenced region doesn't really work. We have no API to configure
+		 * the fence start offset within the object (nor could we probably
+		 * on gen2/3). So it's just easier if we just require that the
+		 * fb layout agrees with the fence layout. We already check that the
+		 * fb stride matches the fence stride elsewhere.
+		 */
+		if (intel_fb->obj->tiling_mode != I915_TILING_NONE &&
+		    (x + width) * cpp > fb->pitches[i]) {
+			DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
+				  i, fb->offsets[i]);
+			return -EINVAL;
+		}
+		/*
 		 * First pixel of the framebuffer from
 		 * the start of the normal gtt mapping.

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