[Intel-gfx] [PATCH 4/5] drm/i915: Use simplest form for flushing the single cacheline in the HWS

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> Rather than call a function to compute the matching cachelines and
> clflush them, just call the clflush *instruction* directly. We also know
> that we can use the unpatched plain clflush rather than the clflushopt
> alternative.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index dfb14bfe5bc8..e2b2dc2c2f49 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -393,8 +393,9 @@ intel_ring_sync_index(struct intel_engine_cs *ring,
>  static inline void
>  intel_flush_status_page(struct intel_engine_cs *ring, int reg)
>  {
> -	drm_clflush_virt_range(&ring->status_page.page_addr[reg],
> -			       sizeof(uint32_t));
> +	mb();

Checkpatch complains about memory barrier without comments.

Don't we need to check cpu_has_clflush?
-Mika

> +	clflush(&ring->status_page.page_addr[reg]);
> +	mb();
>  }
>  
>  static inline u32
> -- 
> 2.7.0
>
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