[Intel-gfx] [PATCH 3/6] drm/i915: enable CSC for pipe C

[Matt Roper]

On Tue, Feb 09, 2016 at 12:19:15PM +0000, Lionel Landwerlin wrote:
> Patch based on a previous series by Shashank Sharma.
> 
> v2: Update contributors

Is this patch actually necessary?  If I recall correctly, _MMIO_PIPE()
will support any number of pipes if the delta between register offsets
for each pipe is constant (in that case, you only need to know the
offset of the first two pipes' registers to calculate the offset of any
subsequent pipe's register).  I think _MMIO_PIPE3 is necessary only if
the difference between register offsets is non-constant and thus all
three offsets need to be specified individually.

Same comment for patch #4 of your series.


Matt

> 
> Signed-off-by: Shashank Sharma <shashank.sharma at intel.com>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Signed-off-by: Kumar, Kiran S <kiran.s.kumar at intel.com>
> Signed-off-by: Kausal Malladi <kausalmalladi at gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 40 +++++++++++++++++++++++++++-------------
>  1 file changed, 27 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 188ad5d..7ba8a99 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7634,19 +7634,33 @@ enum skl_disp_power_wells {
>  #define _PIPE_B_CSC_POSTOFF_ME	0x49144
>  #define _PIPE_B_CSC_POSTOFF_LO	0x49148
>  
> -#define PIPE_CSC_COEFF_RY_GY(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
> -#define PIPE_CSC_COEFF_BY(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
> -#define PIPE_CSC_COEFF_RU_GU(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
> -#define PIPE_CSC_COEFF_BU(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
> -#define PIPE_CSC_COEFF_RV_GV(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
> -#define PIPE_CSC_COEFF_BV(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
> -#define PIPE_CSC_MODE(pipe)		_MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
> -#define PIPE_CSC_PREOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
> -#define PIPE_CSC_PREOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
> -#define PIPE_CSC_PREOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
> -#define PIPE_CSC_POSTOFF_HI(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
> -#define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> -#define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
> +#define _PIPE_C_CSC_COEFF_RY_GY	0x49210
> +#define _PIPE_C_CSC_COEFF_BY	0x49214
> +#define _PIPE_C_CSC_COEFF_RU_GU	0x49218
> +#define _PIPE_C_CSC_COEFF_BU	0x4921c
> +#define _PIPE_C_CSC_COEFF_RV_GV	0x49220
> +#define _PIPE_C_CSC_COEFF_BV	0x49224
> +#define _PIPE_C_CSC_MODE	0x49228
> +#define _PIPE_C_CSC_PREOFF_HI	0x49230
> +#define _PIPE_C_CSC_PREOFF_ME	0x49234
> +#define _PIPE_C_CSC_PREOFF_LO	0x49238
> +#define _PIPE_C_CSC_POSTOFF_HI	0x49240
> +#define _PIPE_C_CSC_POSTOFF_ME	0x49244
> +#define _PIPE_C_CSC_POSTOFF_LO	0x49248
> +
> +#define PIPE_CSC_COEFF_RY_GY(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY, _PIPE_C_CSC_COEFF_RY_GY)
> +#define PIPE_CSC_COEFF_BY(pipe)		_MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY, _PIPE_C_CSC_COEFF_BY)
> +#define PIPE_CSC_COEFF_RU_GU(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU, _PIPE_C_CSC_COEFF_RU_GU)
> +#define PIPE_CSC_COEFF_BU(pipe)		_MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU, _PIPE_C_CSC_COEFF_BU)
> +#define PIPE_CSC_COEFF_RV_GV(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV, _PIPE_C_CSC_COEFF_RV_GV)
> +#define PIPE_CSC_COEFF_BV(pipe)		_MMIO_PIPE3(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV, _PIPE_C_CSC_COEFF_BV)
> +#define PIPE_CSC_MODE(pipe)		_MMIO_PIPE3(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE, _PIPE_C_CSC_MODE)
> +#define PIPE_CSC_PREOFF_HI(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI, _PIPE_C_CSC_PREOFF_HI)
> +#define PIPE_CSC_PREOFF_ME(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME, _PIPE_C_CSC_PREOFF_ME)
> +#define PIPE_CSC_PREOFF_LO(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO, _PIPE_C_CSC_PREOFF_LO)
> +#define PIPE_CSC_POSTOFF_HI(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI, _PIPE_C_CSC_POSTOFF_HI)
> +#define PIPE_CSC_POSTOFF_ME(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME, _PIPE_C_CSC_POSTOFF_ME)
> +#define PIPE_CSC_POSTOFF_LO(pipe)	_MMIO_PIPE3(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO, _PIPE_C_CSC_POSTOFF_LO)
>  
>  /* MIPI DSI registers */
>  
> -- 
> 2.7.0
> 
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-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795