[Intel-gfx] [PATCH 3/4] drm/i915/gen9: Extend dmc debug mask to include cores
Runyan, Arthur J
arthur.j.runyan at intel.com
Thu Feb 18 23:43:47 UTC 2016
>From: Deak, Imre
>The BSpec "Sequence to Allow DC5 or DC6" requires this only for BXT
>(looks like a recent addition to work around something), but it doesn't
>say it's needed for other platforms. The register description doesn't
>make a difference though.
>Perhaps Art has more info on this, adding him.
Only BXT needs it programmed to 1b at the moment. Other products should keep the default.
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