[Intel-gfx] [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio sequence support and gpio table
Jani Nikula
jani.nikula at intel.com
Fri Feb 19 13:36:17 UTC 2016
On Fri, 19 Feb 2016, "Deepak, M" <m.deepak at intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Friday, February 19, 2016 6:51 PM
>> To: Deepak, M <m.deepak at intel.com>; intel-gfx at lists.freedesktop.org
>> Cc: Deepak, M <m.deepak at intel.com>
>> Subject: Re: [Generic GPIO patch 1/3] drm/i915/dsi: Added the generic gpio
>> sequence support and gpio table
>>
>> On Fri, 19 Feb 2016, Deepak M <m.deepak at intel.com> wrote:
>> > The generic gpio is sequence is parsed from the VBT and the GPIO table
>> > is updated with the North core, South core and SUS core elements.
>> >
>> > v2: Move changes in sideband.c file to new patch(Jani), rebase
>> > v3: Moved the Macro`s to intel_dsi_panel_vbt.c (Jani)
>> >
>> > v3 by Jani
>> > - rebase on previous patches
>> > - don't return null on errors
>> >
>> > v4 by Deepak
>> > - rebase
>> > - prefixed the VLV_ to all the GPIO macros
>>
>> There were also versions 4, 5 and 6 by me also. v6 is at
>>
>> http://patchwork.freedesktop.org/patch/msgid/f684304ca297fd3dd325c29a
>> 541b8960fe468b96.1454582914.git.jani.nikula at intel.com
>>
>> You should take that as the basis.
> [Deepak, M] The link points me to the i2c patch not the gpio one.
Doh! Sorry, please disregard that. I'll go grab some more coffee.
BR,
Jani.
>>
>> Also see comments inline.
>>
>> > Signed-off-by: Deepak M <m.deepak at intel.com>
>> > Signed-off-by: Jani Nikula <jani.nikula at intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 6 +
>> > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 606
>> > ++++++++++++++++++++++++++---
>> > 2 files changed, 559 insertions(+), 53 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index 3774870..606dc71 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -620,10 +620,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t
>> reg)
>> > #define IOSF_PORT_FLISDSI 0x1b
>> > #define IOSF_PORT_GPIO_SC 0x48
>> > #define IOSF_PORT_GPIO_SUS 0xa8
>> > +#define IOSF_MAX_GPIO_NUM_NC 26
>> > +#define IOSF_MAX_GPIO_NUM_SC 128
>> > +#define IOSF_MAX_GPIO_NUM 172
>> > #define IOSF_PORT_CCU 0xa9
>> > #define VLV_IOSF_DATA
>> _MMIO(VLV_DISPLAY_BASE + 0x2104)
>> > #define VLV_IOSF_ADDR
>> _MMIO(VLV_DISPLAY_BASE + 0x2108)
>> >
>> > +#define VLV_GPIO_CFG 0x2000CC00
>> > +#define VLV_GPIO_INPUT_DIS 0x04
>> > +
>> > /* See configdb bunit SB addr map */
>> > #define BUNIT_REG_BISOC 0x11
>> >
>> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > index 787f01c..e02e5e0 100644
>> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
>> > @@ -58,30 +58,356 @@ static inline struct vbt_panel
>> > *to_vbt_panel(struct drm_panel *panel)
>> >
>> > #define NS_KHZ_RATIO 1000000
>> >
>> > -#define GPI0_NC_0_HV_DDI0_HPD 0x4130
>> > -#define GPIO_NC_0_HV_DDI0_PAD 0x4138
>> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120
>> > -#define GPIO_NC_1_HV_DDI0_DDC_SDA_PAD 0x4128
>> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110
>> > -#define GPIO_NC_2_HV_DDI0_DDC_SCL_PAD 0x4118
>> > -#define GPIO_NC_3_PANEL0_VDDEN 0x4140
>> > -#define GPIO_NC_3_PANEL0_VDDEN_PAD 0x4148
>> > -#define GPIO_NC_4_PANEL0_BLKEN 0x4150
>> > -#define GPIO_NC_4_PANEL0_BLKEN_PAD 0x4158
>> > -#define GPIO_NC_5_PANEL0_BLKCTL 0x4160
>> > -#define GPIO_NC_5_PANEL0_BLKCTL_PAD 0x4168
>> > -#define GPIO_NC_6_PCONF0 0x4180
>> > -#define GPIO_NC_6_PAD 0x4188
>> > -#define GPIO_NC_7_PCONF0 0x4190
>> > -#define GPIO_NC_7_PAD 0x4198
>> > -#define GPIO_NC_8_PCONF0 0x4170
>> > -#define GPIO_NC_8_PAD 0x4178
>> > -#define GPIO_NC_9_PCONF0 0x4100
>> > -#define GPIO_NC_9_PAD 0x4108
>> > -#define GPIO_NC_10_PCONF0 0x40E0
>> > -#define GPIO_NC_10_PAD 0x40E8
>> > -#define GPIO_NC_11_PCONF0 0x40F0
>> > -#define GPIO_NC_11_PAD 0x40F8
>> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PCONF0 0x4130
>> > +#define VLV_HV_DDI0_HPD_GPIONC_0_PAD 0x4138
>> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0 0x4120
>> > +#define VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD 0x4128
>> > +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0 0x4110
>> > +#define VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD 0x4118
>> > +#define VLV_PANEL0_VDDEN_GPIONC_3_PCONF0 0x4140
>> > +#define VLV_PANEL0_VDDEN_GPIONC_3_PAD 0x4148
>> > +#define VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0 0x4150
>> > +#define VLV_PANEL0_BKLTEN_GPIONC_4_PAD 0x4158
>> > +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0 0x4160
>> > +#define VLV_PANEL0_BKLTCTL_GPIONC_5_PAD 0x4168
>> > +#define VLV_HV_DDI1_HPD_GPIONC_6_PCONF0 0x4180
>> > +#define VLV_HV_DDI1_HPD_GPIONC_6_PAD 0x4188
>> > +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0 0x4190
>> > +#define VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD 0x4198
>> > +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0 0x4170
>> > +#define VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD 0x4178
>> > +#define VLV_PANEL1_VDDEN_GPIONC_9_PCONF0 0x4100
>> > +#define VLV_PANEL1_VDDEN_GPIONC_9_PAD 0x4108
>> > +#define VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0 0x40E0
>> > +#define VLV_PANEL1_BKLTEN_GPIONC_10_PAD 0x40E8
>> > +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0 0x40F0
>> > +#define VLV_PANEL1_BKLTCTL_GPIONC_11_PAD 0x40F8
>> > +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0 0x40C0
>> > +#define VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD 0x40C8
>> > +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0 0x41A0
>> > +#define VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD 0x41A8
>> > +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0 0x41B0
>> > +#define VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD 0x41B8
>> > +#define VLV_GP_CAMERASB00_GPIONC_15_PCONF0 0x4010
>> > +#define VLV_GP_CAMERASB00_GPIONC_15_PAD 0x4018
>> > +#define VLV_GP_CAMERASB01_GPIONC_16_PCONF0 0x4040
>> > +#define VLV_GP_CAMERASB01_GPIONC_16_PAD 0x4048
>> > +#define VLV_GP_CAMERASB02_GPIONC_17_PCONF0 0x4080
>> > +#define VLV_GP_CAMERASB02_GPIONC_17_PAD 0x4088
>> > +#define VLV_GP_CAMERASB03_GPIONC_18_PCONF0 0x40B0
>> > +#define VLV_GP_CAMERASB03_GPIONC_18_PAD 0x40B8
>> > +#define VLV_GP_CAMERASB04_GPIONC_19_PCONF0 0x4000
>> > +#define VLV_GP_CAMERASB04_GPIONC_19_PAD 0x4008
>> > +#define VLV_GP_CAMERASB05_GPIONC_20_PCONF0 0x4030
>> > +#define VLV_GP_CAMERASB05_GPIONC_20_PAD 0x4038
>> > +#define VLV_GP_CAMERASB06_GPIONC_21_PCONF0 0x4060
>> > +#define VLV_GP_CAMERASB06_GPIONC_21_PAD 0x4068
>> > +#define VLV_GP_CAMERASB07_GPIONC_22_PCONF0 0x40A0
>> > +#define VLV_GP_CAMERASB07_GPIONC_22_PAD 0x40A8
>> > +#define VLV_GP_CAMERASB08_GPIONC_23_PCONF0 0x40D0
>> > +#define VLV_GP_CAMERASB08_GPIONC_23_PAD 0x40D8
>> > +#define VLV_GP_CAMERASB09_GPIONC_24_PCONF0 0x4020
>> > +#define VLV_GP_CAMERASB09_GPIONC_24_PAD 0x4028
>> > +#define VLV_GP_CAMERASB10_GPIONC_25_PCONF0 0x4050
>> > +#define VLV_GP_CAMERASB10_GPIONC_25_PAD 0x4058
>> > +#define VLV_GP_CAMERASB11_GPIONC_26_PCONF0 0x4090
>> > +#define VLV_GP_CAMERASB11_GPIONC_26_PAD 0x4098
>> > +
>> > +#define VLV_SATA_GP0_GPIOC_0_PCONF0 0x4550
>> > +#define VLV_SATA_GP0_GPIOC_0_PAD 0x4558
>> > +#define VLV_SATA_GP1_GPIOC_1_PCONF0 0x4590
>> > +#define VLV_SATA_GP1_GPIOC_1_PAD 0x4598
>> > +#define VLV_SATA_LEDN_GPIOC_2_PCONF0 0x45D0
>> > +#define VLV_SATA_LEDN_GPIOC_2_PAD 0x45D8
>> > +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0 0x4600
>> > +#define VLV_PCIE_CLKREQ0B_GPIOC_3_PAD 0x4608
>> > +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0 0x4630
>> > +#define VLV_PCIE_CLKREQ1B_GPIOC_4_PAD 0x4638
>> > +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0 0x4660
>> > +#define VLV_PCIE_CLKREQ2B_GPIOC_5_PAD 0x4668
>> > +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0 0x4620
>> > +#define VLV_PCIE_CLKREQ3B_GPIOC_6_PAD 0x4628
>> > +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0 0x4650
>> > +#define VLV_PCIE_CLKREQ4B_GPIOC_7_PAD 0x4658
>> > +#define VLV_HDA_RSTB_GPIOC_8_PCONF0 0x4220
>> > +#define VLV_HDA_RSTB_GPIOC_8_PAD 0x4228
>> > +#define VLV_HDA_SYNC_GPIOC_9_PCONF0 0x4250
>> > +#define VLV_HDA_SYNC_GPIOC_9_PAD 0x4258
>> > +#define VLV_HDA_CLK_GPIOC_10_PCONF0 0x4240
>> > +#define VLV_HDA_CLK_GPIOC_10_PAD 0x4248
>> > +#define VLV_HDA_SDO_GPIOC_11_PCONF0 0x4260
>> > +#define VLV_HDA_SDO_GPIOC_11_PAD 0x4268
>> > +#define VLV_HDA_SDI0_GPIOC_12_PCONF0 0x4270
>> > +#define VLV_HDA_SDI0_GPIOC_12_PAD 0x4278
>> > +#define VLV_HDA_SDI1_GPIOC_13_PCONF0 0x4230
>> > +#define VLV_HDA_SDI1_GPIOC_13_PAD 0x4238
>> > +#define VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0 0x4280
>> > +#define VLV_HDA_DOCKRSTB_GPIOC_14_PAD 0x4288
>> > +#define VLV_HDA_DOCKENB_GPIOC_15_PCONF0 0x4540
>> > +#define VLV_HDA_DOCKENB_GPIOC_15_PAD 0x4548
>> > +#define VLV_SDMMC1_CLK_GPIOC_16_PCONF0 0x43E0
>> > +#define VLV_SDMMC1_CLK_GPIOC_16_PAD 0x43E8
>> > +#define VLV_SDMMC1_D0_GPIOC_17_PCONF0 0x43D0
>> > +#define VLV_SDMMC1_D0_GPIOC_17_PAD 0x43D8
>> > +#define VLV_SDMMC1_D1_GPIOC_18_PCONF0 0x4400
>> > +#define VLV_SDMMC1_D1_GPIOC_18_PAD 0x4408
>> > +#define VLV_SDMMC1_D2_GPIOC_19_PCONF0 0x43B0
>> > +#define VLV_SDMMC1_D2_GPIOC_19_PAD 0x43B8
>> > +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0 0x4360
>> > +#define VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD 0x4368
>> > +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0 0x4380
>> > +#define VLV_MMC1_D4_SD_WE_GPIOC_21_PAD 0x4388
>> > +#define VLV_MMC1_D5_GPIOC_22_PCONF0 0x43C0
>> > +#define VLV_MMC1_D5_GPIOC_22_PAD 0x43C8
>> > +#define VLV_MMC1_D6_GPIOC_23_PCONF0 0x4370
>> > +#define VLV_MMC1_D6_GPIOC_23_PAD 0x4378
>> > +#define VLV_MMC1_D7_GPIOC_24_PCONF0 0x43F0
>> > +#define VLV_MMC1_D7_GPIOC_24_PAD 0x43F8
>> > +#define VLV_SDMMC1_CMD_GPIOC_25_PCONF0 0x4390
>> > +#define VLV_SDMMC1_CMD_GPIOC_25_PAD 0x4398
>> > +#define VLV_MMC1_RESET_B_GPIOC_26_PCONF0 0x4330
>> > +#define VLV_MMC1_RESET_B_GPIOC_26_PAD 0x4338
>> > +#define VLV_SDMMC2_CLK_GPIOC_27_PCONF0 0x4320
>> > +#define VLV_SDMMC2_CLK_GPIOC_27_PAD 0x4328
>> > +#define VLV_SDMMC2_D0_GPIOC_28_PCONF0 0x4350
>> > +#define VLV_SDMMC2_D0_GPIOC_28_PAD 0x4358
>> > +#define VLV_SDMMC2_D1_GPIOC_29_PCONF0 0x42F0
>> > +#define VLV_SDMMC2_D1_GPIOC_29_PAD 0x42F8
>> > +#define VLV_SDMMC2_D2_GPIOC_30_PCONF0 0x4340
>> > +#define VLV_SDMMC2_D2_GPIOC_30_PAD 0x4348
>> > +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0 0x4310
>> > +#define VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD 0x4318
>> > +#define VLV_SDMMC2_CMD_GPIOC_32_PCONF0 0x4300
>> > +#define VLV_SDMMC2_CMD_GPIOC_32_PAD 0x4308
>> > +#define VLV_SDMMC3_CLK_GPIOC_33_PCONF0 0x42B0
>> > +#define VLV_SDMMC3_CLK_GPIOC_33_PAD 0x42B8
>> > +#define VLV_SDMMC3_D0_GPIOC_34_PCONF0 0x42E0
>> > +#define VLV_SDMMC3_D0_GPIOC_34_PAD 0x42E8
>> > +#define VLV_SDMMC3_D1_GPIOC_35_PCONF0 0x4290
>> > +#define VLV_SDMMC3_D1_GPIOC_35_PAD 0x4298
>> > +#define VLV_SDMMC3_D2_GPIOC_36_PCONF0 0x42D0
>> > +#define VLV_SDMMC3_D2_GPIOC_36_PAD 0x42D8
>> > +#define VLV_SDMMC3_D3_GPIOC_37_PCONF0 0x42A0
>> > +#define VLV_SDMMC3_D3_GPIOC_37_PAD 0x42A8
>> > +#define VLV_SDMMC3_CD_B_GPIOC_38_PCONF0 0x43A0
>> > +#define VLV_SDMMC3_CD_B_GPIOC_38_PAD 0x43A8
>> > +#define VLV_SDMMC3_CMD_GPIOC_39_PCONF0 0x42C0
>> > +#define VLV_SDMMC3_CMD_GPIOC_39_PAD 0x42C8
>> > +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0 0x45F0
>> > +#define VLV_SDMMC3_1P8_EN_GPIOC_40_PAD 0x45F8
>> > +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0 0x4690
>> > +#define VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD 0x4698
>> > +#define VLV_LPC_AD0_GPIOC_42_PCONF0 0x4460
>> > +#define VLV_LPC_AD0_GPIOC_42_PAD 0x4468
>> > +#define VLV_LPC_AD1_GPIOC_43_PCONF0 0x4440
>> > +#define VLV_LPC_AD1_GPIOC_43_PAD 0x4448
>> > +#define VLV_LPC_AD2_GPIOC_44_PCONF0 0x4430
>> > +#define VLV_LPC_AD2_GPIOC_44_PAD 0x4438
>> > +#define VLV_LPC_AD3_GPIOC_45_PCONF0 0x4420
>> > +#define VLV_LPC_AD3_GPIOC_45_PAD 0x4428
>> > +#define VLV_LPC_FRAMEB_GPIOC_46_PCONF0 0x4450
>> > +#define VLV_LPC_FRAMEB_GPIOC_46_PAD 0x4458
>> > +#define VLV_LPC_CLKOUT0_GPIOC_47_PCONF0 0x4470
>> > +#define VLV_LPC_CLKOUT0_GPIOC_47_PAD 0x4478
>> > +#define VLV_LPC_CLKOUT1_GPIOC_48_PCONF0 0x4410
>> > +#define VLV_LPC_CLKOUT1_GPIOC_48_PAD 0x4418
>> > +#define VLV_LPC_CLKRUNB_GPIOC_49_PCONF0 0x4480
>> > +#define VLV_LPC_CLKRUNB_GPIOC_49_PAD 0x4488
>> > +#define VLV_ILB_SERIRQ_GPIOC_50_PCONF0 0x4560
>> > +#define VLV_ILB_SERIRQ_GPIOC_50_PAD 0x4568
>> > +#define VLV_SMB_DATA_GPIOC_51_PCONF0 0x45A0
>> > +#define VLV_SMB_DATA_GPIOC_51_PAD 0x45A8
>> > +#define VLV_SMB_CLK_GPIOC_52_PCONF0 0x4580
>> > +#define VLV_SMB_CLK_GPIOC_52_PAD 0x4588
>> > +#define VLV_SMB_ALERTB_GPIOC_53_PCONF0 0x45C0
>> > +#define VLV_SMB_ALERTB_GPIOC_53_PAD 0x45C8
>> > +#define VLV_SPKR_GPIOC_54_PCONF0 0x4670
>> > +#define VLV_SPKR_GPIOC_54_PAD 0x4678
>> > +#define VLV_MHSI_ACDATA_GPIOC_55_PCONF0 0x44D0
>> > +#define VLV_MHSI_ACDATA_GPIOC_55_PAD 0x44D8
>> > +#define VLV_MHSI_ACFLAG_GPIOC_56_PCONF0 0x44F0
>> > +#define VLV_MHSI_ACFLAG_GPIOC_56_PAD 0x44F8
>> > +#define VLV_MHSI_ACREADY_GPIOC_57_PCONF0 0x4530
>> > +#define VLV_MHSI_ACREADY_GPIOC_57_PAD 0x4538
>> > +#define VLV_MHSI_ACWAKE_GPIOC_58_PCONF0 0x44E0
>> > +#define VLV_MHSI_ACWAKE_GPIOC_58_PAD 0x44E8
>> > +#define VLV_MHSI_CADATA_GPIOC_59_PCONF0 0x4510
>> > +#define VLV_MHSI_CADATA_GPIOC_59_PAD 0x4518
>> > +#define VLV_MHSI_CAFLAG_GPIOC_60_PCONF0 0x4500
>> > +#define VLV_MHSI_CAFLAG_GPIOC_60_PAD 0x4508
>> > +#define VLV_MHSI_CAREADY_GPIOC_61_PCONF0 0x4520
>> > +#define VLV_MHSI_CAREADY_GPIOC_61_PAD 0x4528
>> > +#define VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0 0x40D0
>> > +#define VLV_GP_SSP_2_CLK_GPIOC_62_PAD 0x40D8
>> > +#define VLV_GP_SSP_2_FS_GPIOC_63_PCONF0 0x40C0
>> > +#define VLV_GP_SSP_2_FS_GPIOC_63_PAD 0x40C8
>> > +#define VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0 0x40F0
>> > +#define VLV_GP_SSP_2_RXD_GPIOC_64_PAD 0x40F8
>> > +#define VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0 0x40E0
>> > +#define VLV_GP_SSP_2_TXD_GPIOC_65_PAD 0x40E8
>> > +#define VLV_SPI1_CS0_B_GPIOC_66_PCONF0 0x4110
>> > +#define VLV_SPI1_CS0_B_GPIOC_66_PAD 0x4118
>> > +#define VLV_SPI1_MISO_GPIOC_67_PCONF0 0x4120
>> > +#define VLV_SPI1_MISO_GPIOC_67_PAD 0x4128
>> > +#define VLV_SPI1_MOSI_GPIOC_68_PCONF0 0x4130
>> > +#define VLV_SPI1_MOSI_GPIOC_68_PAD 0x4138
>> > +#define VLV_SPI1_CLK_GPIOC_69_PCONF0 0x4100
>> > +#define VLV_SPI1_CLK_GPIOC_69_PAD 0x4108
>> > +#define VLV_UART1_RXD_GPIOC_70_PCONF0 0x4020
>> > +#define VLV_UART1_RXD_GPIOC_70_PAD 0x4028
>> > +#define VLV_UART1_TXD_GPIOC_71_PCONF0 0x4010
>> > +#define VLV_UART1_TXD_GPIOC_71_PAD 0x4018
>> > +#define VLV_UART1_RTS_B_GPIOC_72_PCONF0 0x4000
>> > +#define VLV_UART1_RTS_B_GPIOC_72_PAD 0x4008
>> > +#define VLV_UART1_CTS_B_GPIOC_73_PCONF0 0x4040
>> > +#define VLV_UART1_CTS_B_GPIOC_73_PAD 0x4048
>> > +#define VLV_UART2_RXD_GPIOC_74_PCONF0 0x4060
>> > +#define VLV_UART2_RXD_GPIOC_74_PAD 0x4068
>> > +#define VLV_UART2_TXD_GPIOC_75_PCONF0 0x4070
>> > +#define VLV_UART2_TXD_GPIOC_75_PAD 0x4078
>> > +#define VLV_UART2_RTS_B_GPIOC_76_PCONF0 0x4090
>> > +#define VLV_UART2_RTS_B_GPIOC_76_PAD 0x4098
>> > +#define VLV_UART2_CTS_B_GPIOC_77_PCONF0 0x4080
>> > +#define VLV_UART2_CTS_B_GPIOC_77_PAD 0x4088
>> > +#define VLV_I2C0_SDA_GPIOC_78_PCONF0 0x4210
>> > +#define VLV_I2C0_SDA_GPIOC_78_PAD 0x4218
>> > +#define VLV_I2C0_SCL_GPIOC_79_PCONF0 0x4200
>> > +#define VLV_I2C0_SCL_GPIOC_79_PAD 0x4208
>> > +#define VLV_I2C1_SDA_GPIOC_80_PCONF0 0x41F0
>> > +#define VLV_I2C1_SDA_GPIOC_80_PAD 0x41F8
>> > +#define VLV_I2C1_SCL_GPIOC_81_PCONF0 0x41E0
>> > +#define VLV_I2C1_SCL_GPIOC_81_PAD 0x41E8
>> > +#define VLV_I2C2_SDA_GPIOC_82_PCONF0 0x41D0
>> > +#define VLV_I2C2_SDA_GPIOC_82_PAD 0x41D8
>> > +#define VLV_I2C2_SCL_GPIOC_83_PCONF0 0x41B0
>> > +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
>> > +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
>> > +#define VLV_I2C2_SCL_GPIOC_83_PAD 0x41B8
>> > +#define VLV_I2C3_SDA_GPIOC_84_PCONF0 0x4190
>> > +#define VLV_I2C3_SDA_GPIOC_84_PAD 0x4198
>> > +#define VLV_I2C3_SCL_GPIOC_85_PCONF0 0x41C0
>> > +#define VLV_I2C3_SCL_GPIOC_85_PAD 0x41C8
>> > +#define VLV_I2C4_SDA_GPIOC_86_PCONF0 0x41A0
>> > +#define VLV_I2C4_SDA_GPIOC_86_PAD 0x41A8
>> > +#define VLV_I2C4_SCL_GPIOC_87_PCONF0 0x4170
>> > +#define VLV_I2C4_SCL_GPIOC_87_PAD 0x4178
>> > +#define VLV_I2C5_SDA_GPIOC_88_PCONF0 0x4150
>> > +#define VLV_I2C5_SDA_GPIOC_88_PAD 0x4158
>> > +#define VLV_I2C5_SCL_GPIOC_89_PCONF0 0x4140
>> > +#define VLV_I2C5_SCL_GPIOC_89_PAD 0x4148
>> > +#define VLV_I2C6_SDA_GPIOC_90_PCONF0 0x4180
>> > +#define VLV_I2C6_SDA_GPIOC_90_PAD 0x4188
>> > +#define VLV_I2C6_SCL_GPIOC_91_PCONF0 0x4160
>> > +#define VLV_I2C6_SCL_GPIOC_91_PAD 0x4168
>> > +#define VLV_I2C_NFC_SDA_GPIOC_92_PCONF0 0x4050
>> > +#define VLV_I2C_NFC_SDA_GPIOC_92_PAD 0x4058
>> > +#define VLV_I2C_NFC_SCL_GPIOC_93_PCONF0 0x4030
>> > +#define VLV_I2C_NFC_SCL_GPIOC_93_PAD 0x4038
>> > +#define VLV_PWM0_GPIOC_94_PCONF0 0x40A0
>> > +#define VLV_PWM0_GPIOC_94_PAD 0x40A8
>> > +#define VLV_PWM1_GPIOC_95_PCONF0 0x40B0
>> > +#define VLV_PWM1_GPIOC_95_PAD 0x40B8
>> > +#define VLV_PLT_CLK0_GPIOC_96_PCONF0 0x46A0
>> > +#define VLV_PLT_CLK0_GPIOC_96_PAD 0x46A8
>> > +#define VLV_PLT_CLK1_GPIOC_97_PCONF0 0x4570
>> > +#define VLV_PLT_CLK1_GPIOC_97_PAD 0x4578
>> > +#define VLV_PLT_CLK2_GPIOC_98_PCONF0 0x45B0
>> > +#define VLV_PLT_CLK2_GPIOC_98_PAD 0x45B8
>> > +#define VLV_PLT_CLK3_GPIOC_99_PCONF0 0x4680
>> > +#define VLV_PLT_CLK3_GPIOC_99_PAD 0x4688
>> > +#define VLV_PLT_CLK4_GPIOC_100_PCONF0 0x4610
>> > +#define VLV_PLT_CLK4_GPIOC_100_PAD 0x4618
>> > +#define VLV_PLT_CLK5_GPIOC_101_PCONF0 0x4640
>> > +#define VLV_PLT_CLK5_GPIOC_101_PAD 0x4648
>> > +
>> > +#define VLV_GPIO_SUS0_GPIO_SUS0_PCONF0 0x41D0
>> > +#define VLV_GPIO_SUS0_GPIO_SUS0_PAD 0x41D8
>> > +#define VLV_GPIO_SUS1_GPIO_SUS1_PCONF0 0x4210
>> > +#define VLV_GPIO_SUS1_GPIO_SUS1_PAD 0x4218
>> > +#define VLV_GPIO_SUS2_GPIO_SUS2_PCONF0 0x41E0
>> > +#define VLV_GPIO_SUS2_GPIO_SUS2_PAD 0x41E8
>> > +#define VLV_GPIO_SUS3_GPIO_SUS3_PCONF0 0x41F0
>> > +#define VLV_GPIO_SUS3_GPIO_SUS3_PAD 0x41F8
>> > +#define VLV_GPIO_SUS4_GPIO_SUS4_PCONF0 0x4200
>> > +#define VLV_GPIO_SUS4_GPIO_SUS4_PAD 0x4208
>> > +#define VLV_GPIO_SUS5_GPIO_SUS5_PCONF0 0x4220
>> > +#define VLV_GPIO_SUS5_GPIO_SUS5_PAD 0x4228
>> > +#define VLV_GPIO_SUS6_GPIO_SUS6_PCONF0 0x4240
>> > +#define VLV_GPIO_SUS6_GPIO_SUS6_PAD 0x4248
>> > +#define VLV_GPIO_SUS7_GPIO_SUS7_PCONF0 0x4230
>> > +#define VLV_GPIO_SUS7_GPIO_SUS7_PAD 0x4238
>> > +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0 0x4260
>> > +#define VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD 0x4268
>> > +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0 0x4250
>> > +#define VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD 0x4258
>> > +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0 0x4120
>> > +#define VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD 0x4128
>> > +#define VLV_SUSPWRDNACK_GPIOS_11_PCONF0 0x4070
>> > +#define VLV_SUSPWRDNACK_GPIOS_11_PAD 0x4078
>> > +#define VLV_PMU_SUSCLK_GPIOS_12_PCONF0 0x40B0
>> > +#define VLV_PMU_SUSCLK_GPIOS_12_PAD 0x40B8
>> > +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0 0x4140
>> > +#define VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD 0x4148
>> > +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0 0x4110
>> > +#define VLV_PMU_SLP_LAN_B_GPIOS_14_PAD 0x4118
>> > +#define VLV_PMU_WAKE_B_GPIOS_15_PCONF0 0x4010
>> > +#define VLV_PMU_WAKE_B_GPIOS_15_PAD 0x4018
>> > +#define VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0 0x4080
>> > +#define VLV_PMU_PWRBTN_B_GPIOS_16_PAD 0x4088
>> > +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0 0x40A0
>> > +#define VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD 0x40A8
>> > +#define VLV_SUS_STAT_B_GPIOS_18_PCONF0 0x4130
>> > +#define VLV_SUS_STAT_B_GPIOS_18_PAD 0x4138
>> > +#define VLV_USB_OC0_B_GPIOS_19_PCONF0 0x40C0
>> > +#define VLV_USB_OC0_B_GPIOS_19_PAD 0x40C8
>> > +#define VLV_USB_OC1_B_GPIOS_20_PCONF0 0x4000
>> > +#define VLV_USB_OC1_B_GPIOS_20_PAD 0x4008
>> > +#define VLV_SPI_CS1_B_GPIOS_21_PCONF0 0x4020
>> > +#define VLV_SPI_CS1_B_GPIOS_21_PAD 0x4028
>> > +#define VLV_GPIO_DFX0_GPIOS_22_PCONF0 0x4170
>> > +#define VLV_GPIO_DFX0_GPIOS_22_PAD 0x4178
>> > +#define VLV_GPIO_DFX1_GPIOS_23_PCONF0 0x4270
>> > +#define VLV_GPIO_DFX1_GPIOS_23_PAD 0x4278
>> > +#define VLV_GPIO_DFX2_GPIOS_24_PCONF0 0x41C0
>> > +#define VLV_GPIO_DFX2_GPIOS_24_PAD 0x41C8
>> > +#define VLV_GPIO_DFX3_GPIOS_25_PCONF0 0x41B0
>> > +#define VLV_GPIO_DFX3_GPIOS_25_PAD 0x41B8
>> > +#define VLV_GPIO_DFX4_GPIOS_26_PCONF0 0x4160
>> > +#define VLV_GPIO_DFX4_GPIOS_26_PAD 0x4168
>> > +#define VLV_GPIO_DFX5_GPIOS_27_PCONF0 0x4150
>> > +#define VLV_GPIO_DFX5_GPIOS_27_PAD 0x4158
>> > +#define VLV_GPIO_DFX6_GPIOS_28_PCONF0 0x4180
>> > +#define VLV_GPIO_DFX6_GPIOS_28_PAD 0x4188
>> > +#define VLV_GPIO_DFX7_GPIOS_29_PCONF0 0x4190
>> > +#define VLV_GPIO_DFX7_GPIOS_29_PAD 0x4198
>> > +#define VLV_GPIO_DFX8_GPIOS_30_PCONF0 0x41A0
>> > +#define VLV_GPIO_DFX8_GPIOS_30_PAD 0x41A8
>> > +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0 0x4330
>> > +#define VLV_USB_ULPI_0_CLK_GPIOS_31_PAD 0x4338
>> > +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0 0x4380
>> > +#define VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD 0x4388
>> > +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0 0x4360
>> > +#define VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD 0x4368
>> > +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0 0x4310
>> > +#define VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD 0x4318
>> > +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0 0x4370
>> > +#define VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD 0x4378
>> > +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0 0x4300
>> > +#define VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD 0x4308
>> > +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0 0x4390
>> > +#define VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD 0x4398
>> > +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0 0x4320
>> > +#define VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD 0x4328
>> > +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0 0x43A0
>> > +#define VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD 0x43A8
>> > +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0 0x4340
>> > +#define VLV_USB_ULPI_0_DIR_GPIOS_40_PAD 0x4348
>> > +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0 0x4350
>> > +#define VLV_USB_ULPI_0_NXT_GPIOS_41_PAD 0x4358
>> > +#define VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0 0x43B0
>> > +#define VLV_USB_ULPI_0_STP_GPIOS_42_PAD 0x43B8
>> > +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0 0x4280
>> > +#define VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD 0x4288
>> >
>> > struct gpio_table {
>> > u16 function_reg;
>> > @@ -90,18 +416,181 @@ struct gpio_table { };
>> >
>> > static struct gpio_table gtable[] = {
>> > - { GPI0_NC_0_HV_DDI0_HPD, GPIO_NC_0_HV_DDI0_PAD, 0 },
>> > - { GPIO_NC_1_HV_DDI0_DDC_SDA,
>> GPIO_NC_1_HV_DDI0_DDC_SDA_PAD, 0 },
>> > - { GPIO_NC_2_HV_DDI0_DDC_SCL,
>> GPIO_NC_2_HV_DDI0_DDC_SCL_PAD, 0 },
>> > - { GPIO_NC_3_PANEL0_VDDEN, GPIO_NC_3_PANEL0_VDDEN_PAD,
>> 0 },
>> > - { GPIO_NC_4_PANEL0_BLKEN, GPIO_NC_4_PANEL0_BLKEN_PAD, 0
>> },
>> > - { GPIO_NC_5_PANEL0_BLKCTL, GPIO_NC_5_PANEL0_BLKCTL_PAD, 0
>> },
>> > - { GPIO_NC_6_PCONF0, GPIO_NC_6_PAD, 0 },
>> > - { GPIO_NC_7_PCONF0, GPIO_NC_7_PAD, 0 },
>> > - { GPIO_NC_8_PCONF0, GPIO_NC_8_PAD, 0 },
>> > - { GPIO_NC_9_PCONF0, GPIO_NC_9_PAD, 0 },
>> > - { GPIO_NC_10_PCONF0, GPIO_NC_10_PAD, 0},
>> > - { GPIO_NC_11_PCONF0, GPIO_NC_11_PAD, 0}
>> > + { VLV_HV_DDI0_HPD_GPIONC_0_PCONF0,
>> VLV_HV_DDI0_HPD_GPIONC_0_PAD, 0},
>> > + { VLV_HV_DDI0_DDC_SDA_GPIONC_1_PCONF0,
>> VLV_HV_DDI0_DDC_SDA_GPIONC_1_PAD, 0},
>> > + { VLV_HV_DDI0_DDC_SCL_GPIONC_2_PCONF0,
>> VLV_HV_DDI0_DDC_SCL_GPIONC_2_PAD, 0},
>> > + { VLV_PANEL0_VDDEN_GPIONC_3_PCONF0,
>> VLV_PANEL0_VDDEN_GPIONC_3_PAD, 0},
>> > + { VLV_PANEL0_BKLTEN_GPIONC_4_PCONF0,
>> VLV_PANEL0_BKLTEN_GPIONC_4_PAD, 0},
>> > + { VLV_PANEL0_BKLTCTL_GPIONC_5_PCONF0,
>> VLV_PANEL0_BKLTCTL_GPIONC_5_PAD, 0},
>> > + { VLV_HV_DDI1_HPD_GPIONC_6_PCONF0,
>> VLV_HV_DDI1_HPD_GPIONC_6_PAD, 0},
>> > + { VLV_HV_DDI1_DDC_SDA_GPIONC_7_PCONF0,
>> VLV_HV_DDI1_DDC_SDA_GPIONC_7_PAD, 0},
>> > + { VLV_HV_DDI1_DDC_SCL_GPIONC_8_PCONF0,
>> VLV_HV_DDI1_DDC_SCL_GPIONC_8_PAD, 0},
>> > + { VLV_PANEL1_VDDEN_GPIONC_9_PCONF0,
>> VLV_PANEL1_VDDEN_GPIONC_9_PAD, 0},
>> > + { VLV_PANEL1_BKLTEN_GPIONC_10_PCONF0,
>> VLV_PANEL1_BKLTEN_GPIONC_10_PAD, 0},
>> > + { VLV_PANEL1_BKLTCTL_GPIONC_11_PCONF0,
>> VLV_PANEL1_BKLTCTL_GPIONC_11_PAD, 0},
>> > + { VLV_GP_INTD_DSI_TE1_GPIONC_12_PCONF0,
>> VLV_GP_INTD_DSI_TE1_GPIONC_12_PAD, 0},
>> > + { VLV_HV_DDI2_DDC_SDA_GPIONC_13_PCONF0,
>> VLV_HV_DDI2_DDC_SDA_GPIONC_13_PAD, 0},
>> > + { VLV_HV_DDI2_DDC_SCL_GPIONC_14_PCONF0,
>> VLV_HV_DDI2_DDC_SCL_GPIONC_14_PAD, 0},
>> > + { VLV_GP_CAMERASB00_GPIONC_15_PCONF0,
>> VLV_GP_CAMERASB00_GPIONC_15_PAD, 0},
>> > + { VLV_GP_CAMERASB01_GPIONC_16_PCONF0,
>> VLV_GP_CAMERASB01_GPIONC_16_PAD, 0},
>> > + { VLV_GP_CAMERASB02_GPIONC_17_PCONF0,
>> VLV_GP_CAMERASB02_GPIONC_17_PAD, 0},
>> > + { VLV_GP_CAMERASB03_GPIONC_18_PCONF0,
>> VLV_GP_CAMERASB03_GPIONC_18_PAD, 0},
>> > + { VLV_GP_CAMERASB04_GPIONC_19_PCONF0,
>> VLV_GP_CAMERASB04_GPIONC_19_PAD, 0},
>> > + { VLV_GP_CAMERASB05_GPIONC_20_PCONF0,
>> VLV_GP_CAMERASB05_GPIONC_20_PAD, 0},
>> > + { VLV_GP_CAMERASB06_GPIONC_21_PCONF0,
>> VLV_GP_CAMERASB06_GPIONC_21_PAD, 0},
>> > + { VLV_GP_CAMERASB07_GPIONC_22_PCONF0,
>> VLV_GP_CAMERASB07_GPIONC_22_PAD, 0},
>> > + { VLV_GP_CAMERASB08_GPIONC_23_PCONF0,
>> VLV_GP_CAMERASB08_GPIONC_23_PAD, 0},
>> > + { VLV_GP_CAMERASB09_GPIONC_24_PCONF0,
>> VLV_GP_CAMERASB09_GPIONC_24_PAD, 0},
>> > + { VLV_GP_CAMERASB10_GPIONC_25_PCONF0,
>> VLV_GP_CAMERASB10_GPIONC_25_PAD, 0},
>> > + { VLV_GP_CAMERASB11_GPIONC_26_PCONF0,
>> > +VLV_GP_CAMERASB11_GPIONC_26_PAD, 0},
>> > +
>> > + { VLV_SATA_GP0_GPIOC_0_PCONF0,
>> VLV_SATA_GP0_GPIOC_0_PAD, 0},
>> > + { VLV_SATA_GP1_GPIOC_1_PCONF0,
>> VLV_SATA_GP1_GPIOC_1_PAD, 0},
>> > + { VLV_SATA_LEDN_GPIOC_2_PCONF0,
>> VLV_SATA_LEDN_GPIOC_2_PAD, 0},
>> > + { VLV_PCIE_CLKREQ0B_GPIOC_3_PCONF0,
>> VLV_PCIE_CLKREQ0B_GPIOC_3_PAD, 0},
>> > + { VLV_PCIE_CLKREQ1B_GPIOC_4_PCONF0,
>> VLV_PCIE_CLKREQ1B_GPIOC_4_PAD, 0},
>> > + { VLV_PCIE_CLKREQ2B_GPIOC_5_PCONF0,
>> VLV_PCIE_CLKREQ2B_GPIOC_5_PAD, 0},
>> > + { VLV_PCIE_CLKREQ3B_GPIOC_6_PCONF0,
>> VLV_PCIE_CLKREQ3B_GPIOC_6_PAD, 0},
>> > + { VLV_PCIE_CLKREQ4B_GPIOC_7_PCONF0,
>> VLV_PCIE_CLKREQ4B_GPIOC_7_PAD, 0},
>> > + { VLV_HDA_RSTB_GPIOC_8_PCONF0,
>> VLV_HDA_RSTB_GPIOC_8_PAD, 0},
>> > + { VLV_HDA_SYNC_GPIOC_9_PCONF0,
>> VLV_HDA_SYNC_GPIOC_9_PAD, 0},
>> > + { VLV_HDA_CLK_GPIOC_10_PCONF0,
>> VLV_HDA_CLK_GPIOC_10_PAD, 0},
>> > + { VLV_HDA_SDO_GPIOC_11_PCONF0,
>> VLV_HDA_SDO_GPIOC_11_PAD, 0},
>> > + { VLV_HDA_SDI0_GPIOC_12_PCONF0,
>> VLV_HDA_SDI0_GPIOC_12_PAD, 0},
>> > + { VLV_HDA_SDI1_GPIOC_13_PCONF0,
>> VLV_HDA_SDI1_GPIOC_13_PAD, 0},
>> > + { VLV_HDA_DOCKRSTB_GPIOC_14_PCONF0,
>> VLV_HDA_DOCKRSTB_GPIOC_14_PAD, 0},
>> > + { VLV_HDA_DOCKENB_GPIOC_15_PCONF0,
>> VLV_HDA_DOCKENB_GPIOC_15_PAD, 0},
>> > + { VLV_SDMMC1_CLK_GPIOC_16_PCONF0,
>> VLV_SDMMC1_CLK_GPIOC_16_PAD, 0},
>> > + { VLV_SDMMC1_D0_GPIOC_17_PCONF0,
>> VLV_SDMMC1_D0_GPIOC_17_PAD, 0},
>> > + { VLV_SDMMC1_D1_GPIOC_18_PCONF0,
>> VLV_SDMMC1_D1_GPIOC_18_PAD, 0},
>> > + { VLV_SDMMC1_D2_GPIOC_19_PCONF0,
>> VLV_SDMMC1_D2_GPIOC_19_PAD, 0},
>> > + { VLV_SDMMC1_D3_CD_B_GPIOC_20_PCONF0,
>> VLV_SDMMC1_D3_CD_B_GPIOC_20_PAD, 0},
>> > + { VLV_MMC1_D4_SD_WE_GPIOC_21_PCONF0,
>> VLV_MMC1_D4_SD_WE_GPIOC_21_PAD, 0},
>> > + { VLV_MMC1_D5_GPIOC_22_PCONF0,
>> VLV_MMC1_D5_GPIOC_22_PAD, 0},
>> > + { VLV_MMC1_D6_GPIOC_23_PCONF0,
>> VLV_MMC1_D6_GPIOC_23_PAD, 0},
>> > + { VLV_MMC1_D7_GPIOC_24_PCONF0,
>> VLV_MMC1_D7_GPIOC_24_PAD, 0},
>> > + { VLV_SDMMC1_CMD_GPIOC_25_PCONF0,
>> VLV_SDMMC1_CMD_GPIOC_25_PAD, 0},
>> > + { VLV_MMC1_RESET_B_GPIOC_26_PCONF0,
>> VLV_MMC1_RESET_B_GPIOC_26_PAD, 0},
>> > + { VLV_SDMMC2_CLK_GPIOC_27_PCONF0,
>> VLV_SDMMC2_CLK_GPIOC_27_PAD, 0},
>> > + { VLV_SDMMC2_D0_GPIOC_28_PCONF0,
>> VLV_SDMMC2_D0_GPIOC_28_PAD, 0},
>> > + { VLV_SDMMC2_D1_GPIOC_29_PCONF0,
>> VLV_SDMMC2_D1_GPIOC_29_PAD, 0},
>> > + { VLV_SDMMC2_D2_GPIOC_30_PCONF0,
>> VLV_SDMMC2_D2_GPIOC_30_PAD, 0},
>> > + { VLV_SDMMC2_D3_CD_B_GPIOC_31_PCONF0,
>> VLV_SDMMC2_D3_CD_B_GPIOC_31_PAD, 0},
>> > + { VLV_SDMMC2_CMD_GPIOC_32_PCONF0,
>> VLV_SDMMC2_CMD_GPIOC_32_PAD, 0},
>> > + { VLV_SDMMC3_CLK_GPIOC_33_PCONF0,
>> VLV_SDMMC3_CLK_GPIOC_33_PAD, 0},
>> > + { VLV_SDMMC3_D0_GPIOC_34_PCONF0,
>> VLV_SDMMC3_D0_GPIOC_34_PAD, 0},
>> > + { VLV_SDMMC3_D1_GPIOC_35_PCONF0,
>> VLV_SDMMC3_D1_GPIOC_35_PAD, 0},
>> > + { VLV_SDMMC3_D2_GPIOC_36_PCONF0,
>> VLV_SDMMC3_D2_GPIOC_36_PAD, 0},
>> > + { VLV_SDMMC3_D3_GPIOC_37_PCONF0,
>> VLV_SDMMC3_D3_GPIOC_37_PAD, 0},
>> > + { VLV_SDMMC3_CD_B_GPIOC_38_PCONF0,
>> VLV_SDMMC3_CD_B_GPIOC_38_PAD, 0},
>> > + { VLV_SDMMC3_CMD_GPIOC_39_PCONF0,
>> VLV_SDMMC3_CMD_GPIOC_39_PAD, 0},
>> > + { VLV_SDMMC3_1P8_EN_GPIOC_40_PCONF0,
>> VLV_SDMMC3_1P8_EN_GPIOC_40_PAD, 0},
>> > + { VLV_SDMMC3_PWR_EN_B_GPIOC_41_PCONF0,
>> VLV_SDMMC3_PWR_EN_B_GPIOC_41_PAD, 0},
>> > + { VLV_LPC_AD0_GPIOC_42_PCONF0,
>> VLV_LPC_AD0_GPIOC_42_PAD, 0},
>> > + { VLV_LPC_AD1_GPIOC_43_PCONF0,
>> VLV_LPC_AD1_GPIOC_43_PAD, 0},
>> > + { VLV_LPC_AD2_GPIOC_44_PCONF0,
>> VLV_LPC_AD2_GPIOC_44_PAD, 0},
>> > + { VLV_LPC_AD3_GPIOC_45_PCONF0,
>> VLV_LPC_AD3_GPIOC_45_PAD, 0},
>> > + { VLV_LPC_FRAMEB_GPIOC_46_PCONF0,
>> VLV_LPC_FRAMEB_GPIOC_46_PAD, 0},
>> > + { VLV_LPC_CLKOUT0_GPIOC_47_PCONF0,
>> VLV_LPC_CLKOUT0_GPIOC_47_PAD, 0},
>> > + { VLV_LPC_CLKOUT1_GPIOC_48_PCONF0,
>> VLV_LPC_CLKOUT1_GPIOC_48_PAD, 0},
>> > + { VLV_LPC_CLKRUNB_GPIOC_49_PCONF0,
>> VLV_LPC_CLKRUNB_GPIOC_49_PAD, 0},
>> > + { VLV_ILB_SERIRQ_GPIOC_50_PCONF0,
>> VLV_ILB_SERIRQ_GPIOC_50_PAD, 0},
>> > + { VLV_SMB_DATA_GPIOC_51_PCONF0,
>> VLV_SMB_DATA_GPIOC_51_PAD, 0},
>> > + { VLV_SMB_CLK_GPIOC_52_PCONF0,
>> VLV_SMB_CLK_GPIOC_52_PAD, 0},
>> > + { VLV_SMB_ALERTB_GPIOC_53_PCONF0,
>> VLV_SMB_ALERTB_GPIOC_53_PAD, 0},
>> > + { VLV_SPKR_GPIOC_54_PCONF0, VLV_SPKR_GPIOC_54_PAD, 0},
>> > + { VLV_MHSI_ACDATA_GPIOC_55_PCONF0,
>> VLV_MHSI_ACDATA_GPIOC_55_PAD, 0},
>> > + { VLV_MHSI_ACFLAG_GPIOC_56_PCONF0,
>> VLV_MHSI_ACFLAG_GPIOC_56_PAD, 0},
>> > + { VLV_MHSI_ACREADY_GPIOC_57_PCONF0,
>> VLV_MHSI_ACREADY_GPIOC_57_PAD, 0},
>> > + { VLV_MHSI_ACWAKE_GPIOC_58_PCONF0,
>> VLV_MHSI_ACWAKE_GPIOC_58_PAD, 0},
>> > + { VLV_MHSI_CADATA_GPIOC_59_PCONF0,
>> VLV_MHSI_CADATA_GPIOC_59_PAD, 0},
>> > + { VLV_MHSI_CAFLAG_GPIOC_60_PCONF0,
>> VLV_MHSI_CAFLAG_GPIOC_60_PAD, 0},
>> > + { VLV_MHSI_CAREADY_GPIOC_61_PCONF0,
>> VLV_MHSI_CAREADY_GPIOC_61_PAD, 0},
>> > + { VLV_GP_SSP_2_CLK_GPIOC_62_PCONF0,
>> VLV_GP_SSP_2_CLK_GPIOC_62_PAD, 0},
>> > + { VLV_GP_SSP_2_FS_GPIOC_63_PCONF0,
>> VLV_GP_SSP_2_FS_GPIOC_63_PAD, 0},
>> > + { VLV_GP_SSP_2_RXD_GPIOC_64_PCONF0,
>> VLV_GP_SSP_2_RXD_GPIOC_64_PAD, 0},
>> > + { VLV_GP_SSP_2_TXD_GPIOC_65_PCONF0,
>> VLV_GP_SSP_2_TXD_GPIOC_65_PAD, 0},
>> > + { VLV_SPI1_CS0_B_GPIOC_66_PCONF0,
>> VLV_SPI1_CS0_B_GPIOC_66_PAD, 0},
>> > + { VLV_SPI1_MISO_GPIOC_67_PCONF0,
>> VLV_SPI1_MISO_GPIOC_67_PAD, 0},
>> > + { VLV_SPI1_MOSI_GPIOC_68_PCONF0,
>> VLV_SPI1_MOSI_GPIOC_68_PAD, 0},
>> > + { VLV_SPI1_CLK_GPIOC_69_PCONF0,
>> VLV_SPI1_CLK_GPIOC_69_PAD, 0},
>> > + { VLV_UART1_RXD_GPIOC_70_PCONF0,
>> VLV_UART1_RXD_GPIOC_70_PAD, 0},
>> > + { VLV_UART1_TXD_GPIOC_71_PCONF0,
>> VLV_UART1_TXD_GPIOC_71_PAD, 0},
>> > + { VLV_UART1_RTS_B_GPIOC_72_PCONF0,
>> VLV_UART1_RTS_B_GPIOC_72_PAD, 0},
>> > + { VLV_UART1_CTS_B_GPIOC_73_PCONF0,
>> VLV_UART1_CTS_B_GPIOC_73_PAD, 0},
>> > + { VLV_UART2_RXD_GPIOC_74_PCONF0,
>> VLV_UART2_RXD_GPIOC_74_PAD, 0},
>> > + { VLV_UART2_TXD_GPIOC_75_PCONF0,
>> VLV_UART2_TXD_GPIOC_75_PAD, 0},
>> > + { VLV_UART2_RTS_B_GPIOC_76_PCONF0,
>> VLV_UART2_RTS_B_GPIOC_76_PAD, 0},
>> > + { VLV_UART2_CTS_B_GPIOC_77_PCONF0,
>> VLV_UART2_CTS_B_GPIOC_77_PAD, 0},
>> > + { VLV_I2C0_SDA_GPIOC_78_PCONF0,
>> VLV_I2C0_SDA_GPIOC_78_PAD, 0},
>> > + { VLV_I2C0_SCL_GPIOC_79_PCONF0,
>> VLV_I2C0_SCL_GPIOC_79_PAD, 0},
>> > + { VLV_I2C1_SDA_GPIOC_80_PCONF0,
>> VLV_I2C1_SDA_GPIOC_80_PAD, 0},
>> > + { VLV_I2C1_SCL_GPIOC_81_PCONF0,
>> VLV_I2C1_SCL_GPIOC_81_PAD, 0},
>> > + { VLV_I2C2_SDA_GPIOC_82_PCONF0,
>> VLV_I2C2_SDA_GPIOC_82_PAD, 0},
>> > + { VLV_I2C2_SCL_GPIOC_83_PCONF0,
>> VLV_I2C2_SCL_GPIOC_83_PAD, 0},
>> > + { VLV_I2C3_SDA_GPIOC_84_PCONF0,
>> VLV_I2C3_SDA_GPIOC_84_PAD, 0},
>> > + { VLV_I2C3_SCL_GPIOC_85_PCONF0,
>> VLV_I2C3_SCL_GPIOC_85_PAD, 0},
>> > + { VLV_I2C4_SDA_GPIOC_86_PCONF0,
>> VLV_I2C4_SDA_GPIOC_86_PAD, 0},
>> > + { VLV_I2C4_SCL_GPIOC_87_PCONF0,
>> VLV_I2C4_SCL_GPIOC_87_PAD, 0},
>> > + { VLV_I2C5_SDA_GPIOC_88_PCONF0,
>> VLV_I2C5_SDA_GPIOC_88_PAD, 0},
>> > + { VLV_I2C5_SCL_GPIOC_89_PCONF0,
>> VLV_I2C5_SCL_GPIOC_89_PAD, 0},
>> > + { VLV_I2C6_SDA_GPIOC_90_PCONF0,
>> VLV_I2C6_SDA_GPIOC_90_PAD, 0},
>> > + { VLV_I2C6_SCL_GPIOC_91_PCONF0,
>> VLV_I2C6_SCL_GPIOC_91_PAD, 0},
>> > + { VLV_I2C_NFC_SDA_GPIOC_92_PCONF0,
>> VLV_I2C_NFC_SDA_GPIOC_92_PAD, 0},
>> > + { VLV_I2C_NFC_SCL_GPIOC_93_PCONF0,
>> VLV_I2C_NFC_SCL_GPIOC_93_PAD, 0},
>> > + { VLV_PWM0_GPIOC_94_PCONF0, VLV_PWM0_GPIOC_94_PAD, 0},
>> > + { VLV_PWM1_GPIOC_95_PCONF0, VLV_PWM1_GPIOC_95_PAD, 0},
>> > + { VLV_PLT_CLK0_GPIOC_96_PCONF0,
>> VLV_PLT_CLK0_GPIOC_96_PAD, 0},
>> > + { VLV_PLT_CLK1_GPIOC_97_PCONF0,
>> VLV_PLT_CLK1_GPIOC_97_PAD, 0},
>> > + { VLV_PLT_CLK2_GPIOC_98_PCONF0,
>> VLV_PLT_CLK2_GPIOC_98_PAD, 0},
>> > + { VLV_PLT_CLK3_GPIOC_99_PCONF0,
>> VLV_PLT_CLK3_GPIOC_99_PAD, 0},
>> > + { VLV_PLT_CLK4_GPIOC_100_PCONF0,
>> VLV_PLT_CLK4_GPIOC_100_PAD, 0},
>> > + { VLV_PLT_CLK5_GPIOC_101_PCONF0,
>> VLV_PLT_CLK5_GPIOC_101_PAD, 0},
>> > +
>> > + { VLV_GPIO_SUS0_GPIO_SUS0_PCONF0,
>> VLV_GPIO_SUS0_GPIO_SUS0_PAD, 0},
>> > + { VLV_GPIO_SUS1_GPIO_SUS1_PCONF0,
>> VLV_GPIO_SUS1_GPIO_SUS1_PAD, 0},
>> > + { VLV_GPIO_SUS2_GPIO_SUS2_PCONF0,
>> VLV_GPIO_SUS2_GPIO_SUS2_PAD, 0},
>> > + { VLV_GPIO_SUS3_GPIO_SUS3_PCONF0,
>> VLV_GPIO_SUS3_GPIO_SUS3_PAD, 0},
>> > + { VLV_GPIO_SUS4_GPIO_SUS4_PCONF0,
>> VLV_GPIO_SUS4_GPIO_SUS4_PAD, 0},
>> > + { VLV_GPIO_SUS5_GPIO_SUS5_PCONF0,
>> VLV_GPIO_SUS5_GPIO_SUS5_PAD, 0},
>> > + { VLV_GPIO_SUS6_GPIO_SUS6_PCONF0,
>> VLV_GPIO_SUS6_GPIO_SUS6_PAD, 0},
>> > + { VLV_GPIO_SUS7_GPIO_SUS7_PCONF0,
>> VLV_GPIO_SUS7_GPIO_SUS7_PAD, 0},
>> > + { VLV_SEC_GPIO_SUS8_GPIO_SUS8_PCONF0,
>> VLV_SEC_GPIO_SUS8_GPIO_SUS8_PAD, 0},
>> > + { VLV_SEC_GPIO_SUS9_GPIO_SUS9_PCONF0,
>> VLV_SEC_GPIO_SUS9_GPIO_SUS9_PAD, 0},
>> > + { VLV_SEC_GPIO_SUS10_GPIO_SUS10_PCONF0,
>> VLV_SEC_GPIO_SUS10_GPIO_SUS10_PAD, 0},
>> > + { VLV_SUSPWRDNACK_GPIOS_11_PCONF0,
>> VLV_SUSPWRDNACK_GPIOS_11_PAD, 0},
>> > + { VLV_PMU_SUSCLK_GPIOS_12_PCONF0,
>> VLV_PMU_SUSCLK_GPIOS_12_PAD, 0},
>> > + { VLV_PMU_SLP_S0IX_B_GPIOS_13_PCONF0,
>> VLV_PMU_SLP_S0IX_B_GPIOS_13_PAD, 0},
>> > + { VLV_PMU_SLP_LAN_B_GPIOS_14_PCONF0,
>> VLV_PMU_SLP_LAN_B_GPIOS_14_PAD, 0},
>> > + { VLV_PMU_WAKE_B_GPIOS_15_PCONF0,
>> VLV_PMU_WAKE_B_GPIOS_15_PAD, 0},
>> > + { VLV_PMU_PWRBTN_B_GPIOS_16_PCONF0,
>> VLV_PMU_PWRBTN_B_GPIOS_16_PAD, 0},
>> > + { VLV_PMU_WAKE_LAN_B_GPIOS_17_PCONF0,
>> VLV_PMU_WAKE_LAN_B_GPIOS_17_PAD, 0},
>> > + { VLV_SUS_STAT_B_GPIOS_18_PCONF0,
>> VLV_SUS_STAT_B_GPIOS_18_PAD, 0},
>> > + { VLV_USB_OC0_B_GPIOS_19_PCONF0,
>> VLV_USB_OC0_B_GPIOS_19_PAD, 0},
>> > + { VLV_USB_OC1_B_GPIOS_20_PCONF0,
>> VLV_USB_OC1_B_GPIOS_20_PAD, 0},
>> > + { VLV_SPI_CS1_B_GPIOS_21_PCONF0,
>> VLV_SPI_CS1_B_GPIOS_21_PAD, 0},
>> > + { VLV_GPIO_DFX0_GPIOS_22_PCONF0,
>> VLV_GPIO_DFX0_GPIOS_22_PAD, 0},
>> > + { VLV_GPIO_DFX1_GPIOS_23_PCONF0,
>> VLV_GPIO_DFX1_GPIOS_23_PAD, 0},
>> > + { VLV_GPIO_DFX2_GPIOS_24_PCONF0,
>> VLV_GPIO_DFX2_GPIOS_24_PAD, 0},
>> > + { VLV_GPIO_DFX3_GPIOS_25_PCONF0,
>> VLV_GPIO_DFX3_GPIOS_25_PAD, 0},
>> > + { VLV_GPIO_DFX4_GPIOS_26_PCONF0,
>> VLV_GPIO_DFX4_GPIOS_26_PAD, 0},
>> > + { VLV_GPIO_DFX5_GPIOS_27_PCONF0,
>> VLV_GPIO_DFX5_GPIOS_27_PAD, 0},
>> > + { VLV_GPIO_DFX6_GPIOS_28_PCONF0,
>> VLV_GPIO_DFX6_GPIOS_28_PAD, 0},
>> > + { VLV_GPIO_DFX7_GPIOS_29_PCONF0,
>> VLV_GPIO_DFX7_GPIOS_29_PAD, 0},
>> > + { VLV_GPIO_DFX8_GPIOS_30_PCONF0,
>> VLV_GPIO_DFX8_GPIOS_30_PAD, 0},
>> > + { VLV_USB_ULPI_0_CLK_GPIOS_31_PCONF0,
>> VLV_USB_ULPI_0_CLK_GPIOS_31_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA0_GPIOS_32_PCONF0,
>> VLV_USB_ULPI_0_DATA0_GPIOS_32_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA1_GPIOS_33_PCONF0,
>> VLV_USB_ULPI_0_DATA1_GPIOS_33_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA2_GPIOS_34_PCONF0,
>> VLV_USB_ULPI_0_DATA2_GPIOS_34_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA3_GPIOS_35_PCONF0,
>> VLV_USB_ULPI_0_DATA3_GPIOS_35_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA4_GPIOS_36_PCONF0,
>> VLV_USB_ULPI_0_DATA4_GPIOS_36_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA5_GPIOS_37_PCONF0,
>> VLV_USB_ULPI_0_DATA5_GPIOS_37_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA6_GPIOS_38_PCONF0,
>> VLV_USB_ULPI_0_DATA6_GPIOS_38_PAD, 0},
>> > + { VLV_USB_ULPI_0_DATA7_GPIOS_39_PCONF0,
>> VLV_USB_ULPI_0_DATA7_GPIOS_39_PAD, 0},
>> > + { VLV_USB_ULPI_0_DIR_GPIOS_40_PCONF0,
>> VLV_USB_ULPI_0_DIR_GPIOS_40_PAD, 0},
>> > + { VLV_USB_ULPI_0_NXT_GPIOS_41_PCONF0,
>> VLV_USB_ULPI_0_NXT_GPIOS_41_PAD, 0},
>> > + { VLV_USB_ULPI_0_STP_GPIOS_42_PCONF0,
>> VLV_USB_ULPI_0_STP_GPIOS_42_PAD, 0},
>> > + { VLV_USB_ULPI_0_REFCLK_GPIOS_43_PCONF0,
>> > +VLV_USB_ULPI_0_REFCLK_GPIOS_43_PAD, 0}
>> > };
>> >
>> > static inline enum port intel_dsi_seq_port_to_port(u8 port) @@ -201,9
>> > +690,16 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi,
>> const u8 *data)
>> > u8 gpio, action;
>> > u16 function, pad;
>> > u32 val;
>> > + u8 port;
>> > struct drm_device *dev = intel_dsi->base.base.dev;
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> >
>> > + DRM_DEBUG_DRIVER("MIPI: executing gpio element\n");
>> > +
>> > + /*
>> > + * Skipping the first byte as it is of no
>> > + * interest for android in new version
>> > + */
>>
> [Deepak, M] Okay, will remove this comment.
>
>> That comment is unnecessary and misleading.
>>
>> > if (dev_priv->vbt.dsi.seq_version >= 3)
>> > data++;
>> >
>> > @@ -212,19 +708,24 @@ static const u8 *mipi_exec_gpio(struct intel_dsi
>> *intel_dsi, const u8 *data)
>> > /* pull up/down */
>> > action = *data++ & 1;
>> >
>> > - if (gpio >= ARRAY_SIZE(gtable)) {
>> > - DRM_DEBUG_KMS("unknown gpio %u\n", gpio);
>> > - goto out;
>> > - }
>> > -
>> > - if (!IS_VALLEYVIEW(dev_priv)) {
>> > - DRM_DEBUG_KMS("GPIO element not supported on this
>> platform\n");
>> > - goto out;
>> > - }
>>
>> Both of these checks are needed and added for a reason.
> [Deepak, M] Okay will add these checks back.
>>
>> > -
>> > if (dev_priv->vbt.dsi.seq_version >= 3) {
>> > - DRM_DEBUG_KMS("GPIO element v3 not supported\n");
>> > - goto out;
>> > + if (gpio <= IOSF_MAX_GPIO_NUM_NC) {
>> > + DRM_DEBUG_DRIVER("GPIO is in the north
>> Block\n");
>> > + port = IOSF_PORT_GPIO_NC;
>> > + } else if (gpio > IOSF_MAX_GPIO_NUM_NC &&
>> > + gpio <= IOSF_MAX_GPIO_NUM_SC)
>> {
>> > + DRM_DEBUG_DRIVER("GPIO is in the south
>> Block\n");
>> > + port = IOSF_PORT_GPIO_SC;
>> > + } else if (gpio > IOSF_MAX_GPIO_NUM_SC &&
>> > + gpio <= IOSF_MAX_GPIO_NUM) {
>> > + DRM_DEBUG_DRIVER("GPIO is in the SUS Block\n");
>> > + port = IOSF_PORT_GPIO_SUS;
>> > + } else {
>> > + DRM_ERROR("GPIO number is not present in the
>> table\n");
>> > + goto out;
>> > + }
>> > + } else {
>> > + port = IOSF_PORT_GPIO_NC;
>> > }
>> >
>> > function = gtable[gpio].function_reg; @@ -233,16 +734,15 @@ static
>> > const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
>> > mutex_lock(&dev_priv->sb_lock);
>> > if (!gtable[gpio].init) {
>> > /* program the function */
>> > - /* FIXME: remove constant below */
>> > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, function,
>> > - 0x2000CC00);
>> > + vlv_iosf_sb_write(dev_priv, port, function,
>> > + VLV_GPIO_CFG);
>> > gtable[gpio].init = 1;
>> > }
>> >
>> > - val = 0x4 | action;
>> > + val = VLV_GPIO_INPUT_DIS | action;
>> >
>> > /* pull up/down */
>> > - vlv_iosf_sb_write(dev_priv, IOSF_PORT_GPIO_NC, pad, val);
>> > + vlv_iosf_sb_write(dev_priv, port, pad, val);
>> > mutex_unlock(&dev_priv->sb_lock);
>> >
>> > out:
>>
>> --
>> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
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