[Intel-gfx] [PATCH] igt/gem_trtt: Exercise the TRTT hardware
kevin.tian at intel.com
Mon Jan 11 22:00:12 PST 2016
> From: akash.goel at intel.com
> Sent: Saturday, January 09, 2016 7:32 PM
> There is a provision to keep TR-TT Tables in virtual space, where the pages of
> TRTT tables will be mapped to PPGTT. This is the adopted mode, as in this mode
> UMD will have a full control on TR-TT management, with bare minimum support
> from KMD.
> So the entries of L3 table will contain the PPGTT offset of L2 Table pages,
> similarly entries of L2 table will contain the PPGTT offset of L1 Table pages.
> The entries of L1 table will contain the PPGTT offset of BOs actually backing
> the Sparse resources.
Just a side note. Using virtual address for TRTT table also benefits virtualization
side. This way we can let guest own TRTT completely. Otherwise we have to
virtualize TRTT table if physical address is used, which is very complex and
could bring obvious performance impact.
It's appreciated if you can add this virtualization requirement in code comment
so others can catch this limitation if they want to do some change in the future. :-)
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