[Intel-gfx] [PATCH 021/190] drm/i915: Use HWS for seqno tracking everywhere

[Chris Wilson]

On Tue, Jan 12, 2016 at 12:05:06PM +0200, Mika Kuoppala wrote:
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> > -	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> > -			PIPE_CONTROL_WRITE_FLUSH |
> > -			PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
> > -	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> > -	intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> > +	intel_ring_emit(ring,
> > +			GFX_OP_PIPE_CONTROL(4) |
> > +			PIPE_CONTROL_QW_WRITE |
> > +			PIPE_CONTROL_WRITE_FLUSH);
> 
> Why no more PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE?

I opened vim to add it back in and I coulnd't bring myself to commit
that attrocity.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre