[Intel-gfx] [PATCH v3] drm/i915: Handle PipeC fused off on IVB/HSW/BDW

[Patrik Jakobsson]

On Wed, Jan 13, 2016 at 06:02:52PM +0200, Gabriel Feceoru wrote:
> Some Gen7/8 production parts may have the Display Pipe C fused off.
> In this case, the display hardware will prevent the Pipe C register bit
> from being set to 1.

Please elaborate on what pipe c register bit is prevented from being set.

Thanks
Patrik

> 
> Fixed by adjusting pipe_count to reflect this.
> 
> v2: Rename HSW_PIPE_C_DISABLE to IVB_PIPE_C_DISABLE as it already exists
>     on ivybridge (Ville)
> v3: Remove unnecessary MMIO read, correct the description (Damien)
> 
> Signed-off-by: Gabriel Feceoru <gabriel.feceoru at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 44a896c..dd0d100 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -813,6 +813,9 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
>  		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
>  			DRM_INFO("Display fused off, disabling\n");
>  			info->num_pipes = 0;
> +		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
> +			DRM_INFO("PipeC fused off\n");
> +			info->num_pipes -= 1;
>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0a98889..a182739 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5945,6 +5945,7 @@ enum skl_disp_power_wells {
>  #define  ILK_INTERNAL_GRAPHICS_DISABLE	(1 << 31)
>  #define  ILK_INTERNAL_DISPLAY_DISABLE	(1 << 30)
>  #define  ILK_DISPLAY_DEBUG_DISABLE	(1 << 29)
> +#define  IVB_PIPE_C_DISABLE		(1 << 28)
>  #define  ILK_HDCP_DISABLE		(1 << 25)
>  #define  ILK_eDP_A_DISABLE		(1 << 24)
>  #define  HSW_CDCLK_LIMIT		(1 << 24)
> -- 
> 1.9.1
> 
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