[Intel-gfx] [PATCH 2/3] drm/i915/gen8: add WaIncreaseDefaultTLBEntries

[tim.gore at intel.com]

From: Tim Gore <tim.gore at intel.com>

Add WaIncreaseDefaultTLBEntries:chv,bdw.
This workaround provides significant perfromance boost
for some OpenCL workloads by adjusting the L3_LRA_1_GPGPU
register.
This is for bdw/chv. Further patches will provide the
workaround for other sku's.

Signed-off-by: Tim Gore <tim.gore at intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++++
 drivers/gpu/drm/i915/i915_reg.h     | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fe960d5..be87318 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2140,6 +2140,11 @@ void gtt_write_workarounds(struct drm_device *dev)
 	 * called on driver load and after a GPU reset, so you can place
 	 * workarounds here even if they get overwritten by GPU reset.
 	 */
+	/* WaIncreaseDefaultTLBEntries:chv,bdw */
+	if (IS_BROADWELL(dev))
+		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
+	else if (IS_CHERRYVIEW(dev))
+		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
 }
 
 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a98889..513e2980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8159,4 +8159,9 @@ enum skl_disp_power_wells {
 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
 
+/* gamt regs */
+#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
+#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW  0x67F1427F /* max/min for LRA1/2 */
+#define   GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV  0x5FF101FF /* max/min for LRA1/2 */
+
 #endif /* _I915_REG_H_ */
-- 
1.9.1