[Intel-gfx] [PATCH v2 0/8] Gen9 HW whitelist and Preemption WA patches

Arun Siluvery arun.siluvery at linux.intel.com
Mon Jan 25 10:23:46 PST 2016

On 25/01/2016 18:01, Daniel Vetter wrote:
> On Thu, Jan 21, 2016 at 04:07:22PM +0000, Arun Siluvery wrote:
>> On 21/01/2016 15:17, Chris Wilson wrote:
>>> On Thu, Jan 21, 2016 at 02:00:39PM +0000, Arun Siluvery wrote:
>>>> Resending all patches as told by Daniel because I didn't use correct
>>>> message-id while replying updated version of Patch1 before which means
>>>> patchwork won't pickup and we won't have CI results. Previous updates
>>>> regarding Patch1 are available at https://patchwork.freedesktop.org/patch/70527/
>>>> Some of the WA patches are now reviewed so I added r-b tags for them.
>>>> Reviewed: 1, 2, 3, 5, 6
>>>> Updated: 4 (to address review comment)
>>>> To be reviewed: 4, 7, 8
>>>> Arun Siluvery (8):
>>>>    drm/i915/gen9: Add framework to whitelist specific GPU registers
>>>>    drm/i915/gen9: Add GEN8_CS_CHICKEN1 to HW whitelist
>>>>    drm/i915/gen9: Add HDC_CHICKEN1 to HW whitelist
>>>>    drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 to HW whitelist
>>>>    drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist
>>>>    drm/i915/skl: Add GEN8_L3SQCREG4 to HW whitelist
>>>>    drm/i915/skl: Enable Per context Preemption granularity control
>>>>    drm/i915/gen9: Add WaOCLCoherentLineFlush
>>> With bland changelogs, it is impossible to assess the severity of the
>>> issues being addressed. How many of these do we need to apply to kernel
>>> release to address potential user impact? Which do backporters need?
>>> Are they critical stability fixes or power tuning or enabling for future
>>> features?
>>> -Chris
>> All of these changes are required for Preemption so they affect Gen9 only.
>> The whitelist changes are really to support for preemption WA that are going
>> to be part of UMD. The WA data is sketchy and for some of them hsd links are
>> not available so I don't really know the details.
> Oh, we need pre-empt wa in UMDs? This is going to be a lot of fun to make
> it work in a backwards-compat fashion ... Have you started digging into
> what would be needed for mesa&co?
Yes it is, userspace mainly selects the type of preemption and anything 
HW allows them in the whitelisted registers but I don't know what all 
would be needed.

There is one WA where something need to be cleared in SIP but neither 
mesa nor beignet uses that at the moment.


> -Daniel

More information about the Intel-gfx mailing list