[Intel-gfx] [RFC 0/3] drm/i915: expose fifo pipe underrun counts

[Joe Konno]

From: Joe Konno <joe.konno at intel.com>

In tracking down a watermark bug, I discovered the pch and cpu underrun
interrupt handlers would disable themselves after initial reports to prevent an
interrupt/dmesg storm. Storms are bad, but underrun interrupt handling should
not cease. For my case, I need to be able to count pch and cpu underruns for
each pipe or transcoder. Displaying this information in the 'i915_display_info'
node seemed the best course of action.

In order to do this, however, I had to revisit some long-standing behaviors in
the underrun interrupt handlers. One problem became three. Thanks in advance
for your review and feedback.

Requesting comment on the following solutions I came up with (corresponding to
each patch in the series):

  1. provide simple 'getter' mechanisms for pch and cpu underrun reporting
     ("is it enabled?")-- and base dmesg output on the answer to that question;

  2. don't allow the interrupt handlers to disable or filter themselves (and
     prevent accurate counting); and finally

  3. atomically-incremented pch and cpu underrun counters, with those counters
     displayed in debugfs i915_display_info per-pipe, per-transcoder

For: https://bugs.freedesktop.org/show_bug.cgi?id=93865


Joe Konno (3):
  drm/i915: get cpu, pch underrun reporting state
  drm/i915: do not disable handler after underrun
  drm/i915: add underrun counts to i915_display_info

 drivers/gpu/drm/i915/i915_debugfs.c        |  6 ++-
 drivers/gpu/drm/i915/intel_drv.h           |  4 ++
 drivers/gpu/drm/i915/intel_fifo_underrun.c | 78 ++++++++++++++++++++++++------
 3 files changed, 71 insertions(+), 17 deletions(-)

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2.6.4