[Intel-gfx] [RFC 28/29] drm/i915: gvt: vGPU context switch
Zhi Wang
zhi.a.wang at intel.com
Thu Jan 28 02:21:50 PST 2016
As different VM may configure different render MMIOs when executing workload,
to schedule workloads between different VM, the render MMIOs have to be
switched.
Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
---
drivers/gpu/drm/i915/gvt/Makefile | 2 +-
drivers/gpu/drm/i915/gvt/debug.h | 3 +
drivers/gpu/drm/i915/gvt/gvt.h | 1 +
drivers/gpu/drm/i915/gvt/render.c | 104 +++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gvt/render.h | 31 +++++++++++
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +
6 files changed, 142 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gvt/render.c
create mode 100644 drivers/gpu/drm/i915/gvt/render.h
diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile
index dcaf715..ccb0d32 100644
--- a/drivers/gpu/drm/i915/gvt/Makefile
+++ b/drivers/gpu/drm/i915/gvt/Makefile
@@ -1,7 +1,7 @@
GVT_SOURCE := gvt.o params.o aperture_gm.o mmio.o handlers.o instance.o \
trace_points.o interrupt.o gtt.o cfg_space.o opregion.o utility.o \
fb_decoder.o display.o edid.o control.o execlist.o scheduler.o \
- sched_policy.o
+ sched_policy.o render.o
ccflags-y += -I$(src) -I$(src)/.. -Wall -Werror -Wno-unused-function
i915_gvt-y := $(GVT_SOURCE)
diff --git a/drivers/gpu/drm/i915/gvt/debug.h b/drivers/gpu/drm/i915/gvt/debug.h
index c4c03ac..953ba08 100644
--- a/drivers/gpu/drm/i915/gvt/debug.h
+++ b/drivers/gpu/drm/i915/gvt/debug.h
@@ -87,6 +87,9 @@ enum {
#define gvt_dbg_irq(fmt, args...) \
gvt_dbg(GVT_DBG_IRQ, fmt, ##args)
+#define gvt_dbg_render(fmt, args...) \
+ gvt_dbg(GVT_DBG_RENDER, fmt, ##args)
+
#define gvt_dbg_el(fmt, args...) \
gvt_dbg(GVT_DBG_EL, fmt, ##args)
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 5788bb7..d7ff61e 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -45,6 +45,7 @@
#include "execlist.h"
#include "scheduler.h"
#include "sched_policy.h"
+#include "render.h"
#define GVT_MAX_VGPU 8
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
new file mode 100644
index 0000000..2552c77
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "gvt.h"
+
+struct render_mmio {
+ int ring_id;
+ u32 reg;
+ u32 value;
+ u32 mask;
+};
+
+static struct render_mmio gen8_render_mmio_list[] = {
+ {RCS, 0x229c, 0xffff},
+ {RCS, 0x2248, 0x0},
+ {RCS, 0x2098, 0x0},
+ {RCS, 0x20c0, 0xffff},
+ {RCS, 0x24d0, 0},
+ {RCS, 0x24d4, 0},
+ {RCS, 0x24d8, 0},
+ {RCS, 0x24dc, 0},
+ {RCS, 0x7004, 0xffff},
+ {RCS, 0x7008, 0xffff},
+ {RCS, 0x7000, 0xffff},
+ {RCS, 0x7010, 0xffff},
+ {RCS, 0x7300, 0xffff},
+ {RCS, 0x83a4, 0xffff},
+
+ {BCS, GVT_RING_MODE(BLT_RING_BASE), 0xffff},
+ {BCS, _RING_MI_MODE(BLT_RING_BASE), 0xffff},
+ {BCS, _RING_INSTPM(BLT_RING_BASE), 0xffff},
+ {BCS, _RING_HWSTAM(BLT_RING_BASE), 0xffff},
+ {BCS, 0x22028, 0x0},
+};
+
+void gvt_load_render_mmio(struct vgt_device *vgt, int ring_id)
+{
+ u32 v;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gen8_render_mmio_list); i++) {
+ struct render_mmio *mmio = gen8_render_mmio_list + i;
+ if (mmio->ring_id != ring_id)
+ continue;
+
+ mmio->value = gvt_mmio_read(vgt->pdev, mmio->reg);
+ if (mmio->mask)
+ v = __vreg(vgt, mmio->reg) | (mmio->mask << 16);
+ else
+ v = __vreg(vgt, mmio->reg);
+
+ gvt_mmio_write(vgt->pdev, mmio->reg, v);
+ gvt_mmio_posting_read(vgt->pdev, mmio->reg);
+
+ gvt_dbg_render("reg %x value old %x new %x",
+ mmio->reg, mmio->value, v);
+ }
+}
+
+void gvt_restore_render_mmio(struct vgt_device *vgt, int ring_id)
+{
+ u32 v;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gen8_render_mmio_list); i++) {
+ struct render_mmio *mmio = gen8_render_mmio_list + i;
+ if (mmio->ring_id != ring_id)
+ continue;
+
+ __vreg(vgt, mmio->reg) = gvt_mmio_read(vgt->pdev, mmio->reg);
+
+ if (mmio->mask) {
+ __vreg(vgt, mmio->reg) &= ~(mmio->mask << 16);
+ v = mmio->value | (mmio->mask << 16);
+ } else
+ v = mmio->value;
+
+ gvt_mmio_write(vgt->pdev, mmio->reg, v);
+ gvt_mmio_posting_read(vgt->pdev, mmio->reg);
+
+ gvt_dbg_render("reg %x value old %x new %x",
+ mmio->reg, mmio->value, v);
+ }
+}
diff --git a/drivers/gpu/drm/i915/gvt/render.h b/drivers/gpu/drm/i915/gvt/render.h
new file mode 100644
index 0000000..8058113
--- /dev/null
+++ b/drivers/gpu/drm/i915/gvt/render.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __GVT_RENDER_H__
+#define __GVT_RENDER_H__
+
+void gvt_load_render_mmio(struct vgt_device *vgt, int ring_id);
+
+void gvt_restore_render_mmio(struct vgt_device *vgt, int ring_id);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index d8d2e23..d38aeb1 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -106,6 +106,7 @@ static void shadow_context_schedule_in(void *data)
{
struct gvt_workload *workload = (struct gvt_workload *)data;
+ gvt_load_render_mmio(workload->vgt, workload->ring_id);
atomic_set(&workload->shadow_ctx_active, 1);
wake_up(&workload->shadow_ctx_status_wq);
}
@@ -114,6 +115,7 @@ static void shadow_context_schedule_out(void *data)
{
struct gvt_workload *workload = (struct gvt_workload *)data;
+ gvt_restore_render_mmio(workload->vgt, workload->ring_id);
atomic_set(&workload->shadow_ctx_active, 0);
wake_up(&workload->shadow_ctx_status_wq);
}
--
1.9.1
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