[Intel-gfx] [PATCH 04/14] drm/i915: Support for GuC interrupts

[Chris Wilson]

On Sun, Jul 03, 2016 at 12:21:21AM +0530, akash.goel at intel.com wrote:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 85a7103..20c701c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1808,6 +1808,7 @@ struct drm_i915_private {
>  	u32 pm_irq_mask;
>  	u32 pm_ier_mask;
>  	u32 pm_rps_events;
> +	u32 guc_events;

pm_guc_events so we have some clue as to which register/control block it
is associated within the massive drm_i915_private.

>  	u32 pipestat_irq_mask[I915_MAX_PIPES];
>  
>  	struct i915_hotplug hotplug;
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index fedf82b..b441951 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1038,6 +1038,8 @@ int intel_guc_suspend(struct drm_device *dev)
>  	if (guc->guc_fw.guc_fw_load_status != GUC_FIRMWARE_SUCCESS)
>  		return 0;
>  
> +	gen9_disable_guc_interrupts(dev_priv);

Also upon sanitize?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre