[Intel-gfx] [PATCH 4/5] drm/i915: Make more use of the shared engine irq setup

[Daniel Vetter]

On Fri, Jul 01, 2016 at 05:47:14PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> 
> Use it for legacy engine initialization by adding a
> intel_ring_default_irqs helper used by individual engines.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Not sure this is worth it. irq handling is fairly gen specific, and the
overlap between lrc and legacy rings is just gen8. For preceeding two
patches 2&3:

Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++++++++++++++------------------
>  1 file changed, 16 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a00adc3438f3..964776bb181c 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2394,8 +2394,6 @@ static int intel_init_ring_buffer(struct drm_device *dev,
>  	memset(engine->semaphore.sync_seqno, 0,
>  	       sizeof(engine->semaphore.sync_seqno));
>  
> -	init_waitqueue_head(&engine->irq_queue);
> -
>  	/* We may need to do things with the shrinker which
>  	 * require us to immediately switch back to the default
>  	 * context. This can cause a problem as pinning the
> @@ -3033,6 +3031,13 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
>  	intel_ring_init_semaphores(dev_priv, engine);
>  }
>  
> +static void
> +intel_ring_default_irqs(struct intel_engine_cs *engine)
> +{
> +	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
> +	init_waitqueue_head(&engine->irq_queue);
> +}
> +
>  int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> @@ -3040,12 +3045,12 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>  	int ret;
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
> +	intel_ring_default_irqs(engine);
>  
>  	if (INTEL_GEN(dev_priv) >= 8) {
>  		engine->init_context = intel_rcs_ctx_init;
>  		engine->add_request = gen8_render_add_request;
>  		engine->flush = gen8_render_ring_flush;
> -		engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
>  		if (i915_semaphore_is_enabled(dev_priv))
>  			engine->semaphore.signal = gen8_rcs_signal;
>  	} else if (INTEL_GEN(dev_priv) >= 6) {
> @@ -3053,14 +3058,12 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
>  		engine->flush = gen7_render_ring_flush;
>  		if (IS_GEN6(dev_priv))
>  			engine->flush = gen6_render_ring_flush;
> -		engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
>  	} else if (IS_GEN5(dev_priv)) {
>  		engine->add_request = pc_render_add_request;
>  		engine->flush = gen4_render_ring_flush;
>  		engine->get_seqno = pc_render_get_seqno;
>  		engine->set_seqno = pc_render_set_seqno;
> -		engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
> -					GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
> +		engine->irq_enable_mask |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
>  	} else {
>  		if (INTEL_GEN(dev_priv) < 4)
>  			engine->flush = gen2_render_ring_flush;
> @@ -3112,16 +3115,14 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
> +	intel_ring_default_irqs(engine);
>  
>  	if (INTEL_GEN(dev_priv) >= 6) {
>  		/* gen6 bsd needs a special wa for tail updates */
>  		if (IS_GEN6(dev_priv))
>  			engine->write_tail = gen6_bsd_ring_write_tail;
>  		engine->flush = gen6_bsd_ring_flush;
> -		if (INTEL_GEN(dev_priv) >= 8)
> -			engine->irq_enable_mask =
> -				GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
> -		else
> +		if (INTEL_GEN(dev_priv) < 8)
>  			engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>  	} else {
>  		engine->mmio_base = BSD_RING_BASE;
> @@ -3143,10 +3144,9 @@ int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
> +	intel_ring_default_irqs(engine);
>  
>  	engine->flush = gen6_bsd_ring_flush;
> -	engine->irq_enable_mask =
> -			GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
>  
>  	return intel_init_ring_buffer(dev_priv->dev, engine);
>  }
> @@ -3156,12 +3156,10 @@ int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
> +	intel_ring_default_irqs(engine);
>  
>  	engine->flush = gen6_ring_flush;
> -	if (INTEL_GEN(dev_priv) >= 8)
> -		engine->irq_enable_mask =
> -			GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
> -	else
> +	if (INTEL_GEN(dev_priv) < 8)
>  		engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>  
>  	return intel_init_ring_buffer(dev_priv->dev, engine);
> @@ -3172,13 +3170,11 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  
>  	intel_ring_default_vfuncs(dev_priv, engine);
> +	intel_ring_default_irqs(engine);
>  
>  	engine->flush = gen6_ring_flush;
>  
> -	if (INTEL_GEN(dev_priv) >= 8) {
> -		engine->irq_enable_mask =
> -			GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
> -	} else {
> +	if (INTEL_GEN(dev_priv) < 8) {
>  		engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
>  		engine->irq_get = hsw_vebox_get_irq;
>  		engine->irq_put = hsw_vebox_put_irq;
> -- 
> 1.9.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch