[Intel-gfx] [PATCH 01/23] drm/i915: Move HAS_PSR definition to platform struct definition

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

On Wed, Jul 20, 2016 at 10:40 AM, Carlos Santa <carlos.santa at intel.com> wrote:
> [patch series] Moving all GPU features to the platform struct definition
> allows for
>         - standard place when adding new features from new platforms
>         - possible to see supported features when dumping struct definition
>
> Signed-off-by: Carlos Santa <carlos.santa at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 5 ++---
>  drivers/gpu/drm/i915/i915_pci.c | 5 ++++-
>  2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e76cfe2..6569eb7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -768,6 +768,7 @@ struct intel_csr {
>         func(is_kabylake) sep \
>         func(is_preliminary) sep \
>         func(has_fbc) sep \
> +       func(has_psr) sep \
>         func(has_pipe_cxsr) sep \
>         func(has_hotplug) sep \
>         func(cursor_needs_physical) sep \
> @@ -2846,9 +2847,7 @@ struct drm_i915_cmd_table {
>
>  #define HAS_DDI(dev)           (INTEL_INFO(dev)->has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)    (INTEL_INFO(dev)->has_fpga_dbg)
> -#define HAS_PSR(dev)           (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
> -                                IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
> -                                IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
> +#define HAS_PSR(dev)           (INTEL_INFO(dev)->has_psr)
>  #define HAS_RUNTIME_PM(dev)    (IS_GEN6(dev) || IS_HASWELL(dev) || \
>                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
>                                  IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 949c016..08cdeb3 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -242,6 +242,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
>
>  #define VLV_FEATURES  \
>         .gen = 7, .num_pipes = 2, \
> +       .has_psr = 1, \
>         .need_gfx_hws = 1, .has_hotplug = 1, \
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>         .display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -263,7 +264,8 @@ static const struct intel_device_info intel_valleyview_d_info = {
>         GEN7_FEATURES, \
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
>         .has_ddi = 1, \
> -       .has_fpga_dbg = 1
> +       .has_fpga_dbg = 1, \
> +       .has_psr = 1
>
>  static const struct intel_device_info intel_haswell_d_info = {
>         HSW_FEATURES,
> @@ -311,6 +313,7 @@ static const struct intel_device_info intel_cherryview_info = {
>         .need_gfx_hws = 1, .has_hotplug = 1,
>         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
>         .is_cherryview = 1,
> +       .has_psr = 1,
>         .display_mmio_offset = VLV_DISPLAY_BASE,
>         GEN_CHV_PIPEOFFSETS,
>         CURSOR_OFFSETS,
> --
> 1.9.1
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br