[Intel-gfx] [PATCH v2] drm/i915:gen9: restrict WaC6DisallowByGfxPause

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>

On 7/20/2016 3:30 PM, tim.gore at intel.com wrote:
> From: Tim Gore <tim.gore at intel.com>
>
> WaC6DisallowByGfxPause is currently applied unconditionally
> but is not required in all revisions.
>
> v2: extend application of workaround to agree with w/a
> database, which differs from the HSD.
>
> References: HSD#2133391
> Signed-off-by: Tim Gore <tim.gore at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_guc_loader.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 605c696..96b0259 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -349,7 +349,9 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>   	}
>   
>   	/* WaC6DisallowByGfxPause*/
> -	I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
> +	if (IS_SKL_REVID(dev, 0, SKL_REVID_C0) ||
> +	    IS_BXT_REVID(dev, 0, BXT_REVID_B0))
> +		I915_WRITE(GEN6_GFXPAUSE, 0x30FFF);
>   
>   	if (IS_BROXTON(dev))
>   		I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);