[Intel-gfx] [PATCH 12/18] drm/i915: Unify request submission

Chris Wilson chris at chris-wilson.co.uk
Fri Jul 22 08:24:58 UTC 2016


On Fri, Jul 22, 2016 at 11:03:19AM +0300, Joonas Lahtinen wrote:
> On ke, 2016-07-20 at 14:12 +0100, Chris Wilson wrote:
> > @@ -1904,8 +1898,10 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> >  {
> >  	/* Default vfuncs which can be overriden by each engine. */
> >  	engine->init_hw = gen8_init_common_ring;
> > -	engine->emit_request = gen8_emit_request;
> >  	engine->emit_flush = gen8_emit_flush;
> > +	engine->emit_request = gen8_emit_request;
> > +	engine->submit_request = execlists_context_queue;
> 
> execlists_context_queue name could be changed too, just defined and one
> calling site.

Could, but at the moment execlists_context_queue is paired with
execlists_context_unqueue, and we already have
execlists_submit_requests().

Not that we are queueing contexts either.

Perhaps.

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index a9ca31c113c3..a1908b2caf72 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -384,8 +384,8 @@ static void execlists_update_context(struct drm_i915_gem_request *rq)
                execlists_update_context_pdps(ppgtt, reg_state);
 }
 
-static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
-                                     struct drm_i915_gem_request *rq1)
+static void execlists_submit_elsp(struct drm_i915_gem_request *rq0,
+                                 struct drm_i915_gem_request *rq1)

This is weak. execlists_elsp_submit_contexts?

 {
        struct drm_i915_private *dev_priv = rq0->i915;
        unsigned int fw_domains = rq0->engine->fw_domains;
@@ -418,7 +418,7 @@ static inline void execlists_context_status_change(
        atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
 }
 
-static void execlists_context_unqueue(struct intel_engine_cs *engine)
+static void execlists_unqueue(struct intel_engine_cs *engine)
 {
        struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
        struct drm_i915_gem_request *cursor, *tmp;
@@ -486,7 +486,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
                req0->tail &= req0->ring->size - 1;
        }
 
-       execlists_submit_requests(req0, req1);
+       execlists_submit_elsp(req0, req1);
 }
 
 static unsigned int
@@ -597,7 +597,7 @@ static void intel_lrc_irq_handler(unsigned long data)
        if (submit_contexts) {
                if (!engine->disable_lite_restore_wa ||
                    (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
-                       execlists_context_unqueue(engine);
+                       execlists_unqueue(engine);
        }
 
        spin_unlock(&engine->execlist_lock);
@@ -606,7 +606,7 @@ static void intel_lrc_irq_handler(unsigned long data)
                DRM_ERROR("More than two context complete events?\n");
 }
 
-static void execlists_context_queue(struct drm_i915_gem_request *request)
+static void execlists_submit_request(struct drm_i915_gem_request *request)
 {
        struct intel_engine_cs *engine = request->engine;
        struct drm_i915_gem_request *cursor;
@@ -637,7 +637,7 @@ static void execlists_context_queue(struct drm_i915_gem_request *request)
        list_add_tail(&request->execlist_link, &engine->execlist_queue);
        request->ctx_hw_id = request->ctx->hw_id;
        if (num_elements == 0)
-               execlists_context_unqueue(engine);
+               execlists_unqueue(engine);
 
        spin_unlock_bh(&engine->execlist_lock);
 }
@@ -1908,7 +1908,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
        engine->init_hw = gen8_init_common_ring;
        engine->emit_flush = gen8_emit_flush;
        engine->emit_request = gen8_emit_request;
-       engine->submit_request = execlists_context_queue;
+       engine->submit_request = execlists_submit_request;
 
        engine->irq_enable = gen8_logical_ring_enable_irq;
        engine->irq_disable = gen8_logical_ring_disable_irq;



-- 
Chris Wilson, Intel Open Source Technology Centre


More information about the Intel-gfx mailing list