[Intel-gfx] [PATCH 2/2] drm/i915: Fix use of engine->index for register offset

[Joonas Lahtinen]

On ke, 2016-07-27 at 19:11 +0100, Chris Wilson wrote:
> Since commit de1add360522 ("drm/i915: Decouple execbuf uAPI from internal
> implementation") the index of the engine (its engine->id) in the
> internal list no longer matches the hardware id. However, in a couple of
> locations we missed fixing up the difference. In this case,
> RING_FAULT_REG() refers to engine->id which is now not what the register
> offset actually should be. Fortunately, in both case we should be more
> or less looping over 0..I915_NUM_ENGINES.
> 
> Fixes: de1add360522 ("drm/i915: Decouple execbuf uAPI from internal...")
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>

Seems to be the only instance,

Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>

Regards, Joonas

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9397ddec26b9..3fe75966539d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1647,7 +1647,7 @@ enum skl_disp_power_wells {
>  #define   ARB_MODE_BWGTLB_DISABLE (1<<9)
>  #define   ARB_MODE_SWIZZLE_BDW	(1<<1)
>  #define RENDER_HWS_PGA_GEN7	_MMIO(0x04080)
> -#define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100*(engine)->id)
> +#define RING_FAULT_REG(engine)	_MMIO(0x4094 + 0x100*(engine)->hw_id)
>  #define   RING_FAULT_GTTSEL_MASK (1<<11)
>  #define   RING_FAULT_SRCID(x)	(((x) >> 3) & 0xff)
>  #define   RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation