[Intel-gfx] [PATCH v2 04/21] drm/i915: Move HAS_CORE_RING_FREQ definition to platform definition

[Ville Syrjälä]

On Thu, Jul 28, 2016 at 12:12:19PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> 	- standard place when adding new features from new platforms
> 	- possible to see supported features when dumping struct
> 	  definitions
> 
> Signed-off-by: Carlos Santa <carlos.santa at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 5 ++---
>  drivers/gpu/drm/i915/i915_pci.c | 2 ++
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 69c0196..15e51b8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -774,6 +774,7 @@ struct intel_csr {
>  	func(has_fbc) sep \
>  	func(has_psr) sep \
>  	func(has_runtime_pm) sep \
> +	func(has_core_ring_freq) sep \
>  	func(has_pipe_cxsr) sep \
>  	func(has_hotplug) sep \
>  	func(cursor_needs_physical) sep \
> @@ -2755,9 +2756,7 @@ struct drm_i915_cmd_table {
>  #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
>  				    INTEL_INFO(dev)->gen >= 8)
>  
> -#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
> -				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
> -				 !IS_BROXTON(dev))
> +#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->has_core_ring_freq)
>  
>  #define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
>  
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 92ab3c2..674b298 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -199,6 +199,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.has_fbc = 1, \
>  	.has_runtime_pm = 1, \
> +	.has_core_ring_freq = 1, \

This is actually the same as .has_llc, which makes sense to me since
ring==LLC pretty much. Maybe we should just use that one instead?

>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
> @@ -217,6 +218,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>  	.gen = 7, .num_pipes = 3, \
>  	.need_gfx_hws = 1, .has_hotplug = 1, \
>  	.has_fbc = 1, \
> +	.has_core_ring_freq = 1, \
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
>  	.has_llc = 1, \
>  	GEN_DEFAULT_PIPEOFFSETS, \
> -- 
> 1.9.1
> 
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-- 
Ville Syrjälä
Intel OTC