[Intel-gfx] [PATCH v2 3/3] drm/i915/bxt: Add WaDisablePooledEuLoadBalancingFix

[Mika Kuoppala]

Arun Siluvery <arun.siluvery at linux.intel.com> writes:

> [ text/plain ]
> This is a WA affecting pooled eu which is a bxt specific feature.
>
> Cc: Winiarski, Michal <michal.winiarski at intel.com>
> Cc: Zou, Nanhai <nanhai.zou at intel.com>
> Cc: Yang, Rong R <rong.r.yang at intel.com>
> Cc: Jeff McGee <jeff.mcgee at intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery at linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 1 +
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1d97321e..5268aed 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
>  
>  #define FF_SLICE_CS_CHICKEN2			_MMIO(0x20e4)
>  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
> +#define  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE  (1<<10)
>  
>  #define GEN9_CS_DEBUG_MODE1		_MMIO(0x20ec)
>  #define GEN8_CS_CHICKEN1		_MMIO(0x2580)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d35a39..a21eced 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1145,6 +1145,12 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  STALL_DOP_GATING_DISABLE);
>  
> +	/* WaDisablePooledEuLoadBalancingFix:bxt */
> +	if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
> +		WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
> +				  GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
> +	}
> +
>  	/* WaDisableSbeCacheDispatchPortSharing:bxt */
>  	if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
>  		WA_SET_BIT_MASKED(
> -- 
> 1.9.1
>
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