[Intel-gfx] [PATCH v3] drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate

[Arun Siluvery]

On 13/06/2016 16:45, tim.gore at intel.com wrote:
> From: Tim Gore <tim.gore at intel.com>
>
> This patch enables a workaround for a mid thread preemption
> issue where a hardware timing problem can prevent the
> context restore from happening, leading to a hang.
>
> v2: move to gen9_init_workarounds (Arun)
> v3: move to start of gen9_init_workarounds (Arun)
>
> Signed-off-by: Tim Gore <tim.gore at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 4 ++++
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
>   2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 81d1896..2a6fc62 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1810,6 +1810,10 @@ enum skl_disp_power_wells {
>   #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
>   #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
>
> +/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
> +#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
> +#define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
> +
>   /* WaClearTdlStateAckDirtyBits */
>   #define GEN8_STATE_ACK		_MMIO(0x20F0)
>   #define GEN9_STATE_ACK_SLICE1	_MMIO(0x20F8)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index cf8d0bf..110c7fc 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -910,6 +910,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>   	struct drm_i915_private *dev_priv = engine->i915;
>   	int ret;
>
> +	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
> +	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
> +
agrees with spec. It would've been good to have correct spelling but to 
match with existing documentation we have to use the same name.

Reviewed-by: Arun Siluvery <arun.siluvery at linux.intel.com>

regards
Arun

>   	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
>   	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
>   		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
>