[Intel-gfx] ✗ Ro.CI.BAT: failure for series starting with [v2,RESEND,1/6] drm/i915/bxt: Wait for PHY1 GRC calibration synchronously
Patchwork
patchwork at emeril.freedesktop.org
Mon Jun 13 14:23:34 UTC 2016
== Series Details ==
Series: series starting with [v2,RESEND,1/6] drm/i915/bxt: Wait for PHY1 GRC calibration synchronously
URL : https://patchwork.freedesktop.org/series/8627/
State : failure
== Summary ==
Series 8627v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/8627/revisions/1/mbox
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-cmd:
pass -> FAIL (ro-byt-n2820)
fi-bdw-i7-5557u total:213 pass:201 dwarn:0 dfail:0 fail:0 skip:12
fi-skl-i7-6700k total:213 pass:188 dwarn:0 dfail:0 fail:0 skip:25
ro-bdw-i5-5250u total:213 pass:197 dwarn:2 dfail:0 fail:0 skip:14
ro-bdw-i7-5557U total:213 pass:198 dwarn:1 dfail:0 fail:0 skip:14
ro-bdw-i7-5600u total:213 pass:185 dwarn:0 dfail:0 fail:0 skip:28
ro-bsw-n3050 total:213 pass:171 dwarn:1 dfail:0 fail:2 skip:39
ro-byt-n2820 total:213 pass:173 dwarn:0 dfail:0 fail:3 skip:37
ro-hsw-i3-4010u total:213 pass:190 dwarn:0 dfail:0 fail:0 skip:23
ro-hsw-i7-4770r total:213 pass:190 dwarn:0 dfail:0 fail:0 skip:23
ro-ilk-i7-620lm total:213 pass:150 dwarn:0 dfail:0 fail:1 skip:62
ro-ilk1-i5-650 total:208 pass:150 dwarn:0 dfail:0 fail:1 skip:57
ro-ivb-i7-3770 total:213 pass:181 dwarn:0 dfail:0 fail:0 skip:32
ro-ivb2-i7-3770 total:213 pass:185 dwarn:0 dfail:0 fail:0 skip:28
ro-skl3-i5-6260u total:213 pass:201 dwarn:1 dfail:0 fail:0 skip:11
ro-snb-i7-2620M total:213 pass:174 dwarn:0 dfail:0 fail:1 skip:38
fi-hsw-i7-4770k failed to connect after reboot
fi-skl-i5-6260u failed to connect after reboot
fi-snb-i7-2600 failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1176/
9dfa9b5 drm-intel-nightly: 2016y-06m-13d-13h-48m-21s UTC integration manifest
361caba drm/i915/bxt: Sanitiy check the PHY lane power down status
ab4f3b4 drm/i915/bxt: Rename broxton to bxt in PHY/CDCLK function prefixes
d130ab9 drm/i915/bxt: Set DDI PHY lane latency optimization during modeset
aeba9cb drm/i915/bxt: Move DDI PHY enabling/disabling to the power well code
4d8024d drm/i915: Factor out intel_power_well_get/put
db93190 drm/i915/bxt: Wait for PHY1 GRC calibration synchronously
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