[Intel-gfx] [PATCH v3] drm/i915/fbc: FBC causes display flicker when VT-d is enabled on Skylake

[Daniel Vetter]

On Tue, Jun 21, 2016 at 08:25:27AM +0100, Chris Wilson wrote:
> Erratum SKL075: Display Flicker May Occur When Both VT-d And FBC Are Enabled
> 
> "Display flickering may occur when both FBC (Frame Buffer Compression)
> and VT - d (Intel® Virtualization Technology for Directed I/O) are enabled
> and in use by the display controller."
> 
> Ville found the w/a name in the database:
> WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl
> 
> v2: Log when the quirk is applied.
> v3: Ensure i915.enable_fbc is false when !HAS_FBC()
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>

Do we know whether this helps on other machines too? I can imagine that
the additional lookup latency just plain wreaks havoc everywhere ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
>  drivers/gpu/drm/i915/intel_fbc.c | 19 +++++++++++++++++++
>  2 files changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 89298d3ad94b..f1e9fd07d441 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2586,6 +2586,8 @@ struct drm_i915_cmd_table {
>  #define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
>  #define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
>  
> +#define mkwrite_intel_info(p) ((struct intel_device_info *)INTEL_INFO(p))
> +
>  #define REVID_FOREVER		0xff
>  #define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
>  
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index ac26aa8be9d0..fd5865d80bec 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -1238,12 +1238,28 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
>  	if (i915.enable_fbc >= 0)
>  		return !!i915.enable_fbc;
>  
> +	if (!HAS_FBC(dev_priv))
> +		return 0;
> +
>  	if (IS_BROADWELL(dev_priv))
>  		return 1;
>  
>  	return 0;
>  }
>  
> +static bool need_fbc_wa(struct drm_i915_private *dev_priv)
> +{
> +#ifdef CONFIG_INTEL_IOMMU
> +	/* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl */
> +	if (intel_iommu_gfx_mapped && IS_SKYLAKE(dev_priv)) {
> +		DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
> +		return true;
> +	}
> +#endif
> +
> +	return false;
> +}
> +
>  /**
>   * intel_fbc_init - Initialize FBC
>   * @dev_priv: the i915 device
> @@ -1261,6 +1277,9 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
>  	fbc->active = false;
>  	fbc->work.scheduled = false;
>  
> +	if (need_fbc_wa(dev_priv))
> +		mkwrite_intel_info(dev_priv)->has_fbc = false;
> +
>  	i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
>  	DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
>  
> -- 
> 2.8.1
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch