[Intel-gfx] [PATCH i-g-t 3/3] tools/intel_reg: add initial reg spec for broxton
Jani Nikula
jani.nikula at intel.com
Wed Jun 29 10:06:19 UTC 2016
Mostly just copy SKL, which is probably partly bogus for BXT, but better
than nothing. Add the defs for BXT DSI, but don't dump them by default
because reading them without proper power well and/or DSI PLL may hang
the machine.
Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
tools/registers/broxton | 6 +++
tools/registers/bxt_dsi.txt | 119 ++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 125 insertions(+)
create mode 100644 tools/registers/broxton
create mode 100644 tools/registers/bxt_dsi.txt
diff --git a/tools/registers/broxton b/tools/registers/broxton
new file mode 100644
index 000000000000..4d6345baddbf
--- /dev/null
+++ b/tools/registers/broxton
@@ -0,0 +1,6 @@
+gen8_interrupt.txt
+gen8_other.txt
+skl_powerwells.txt
+skl_display.txt
+# Skip DSI for now.
+# bxt_dsi.txt
diff --git a/tools/registers/bxt_dsi.txt b/tools/registers/bxt_dsi.txt
new file mode 100644
index 000000000000..f0687082b6c8
--- /dev/null
+++ b/tools/registers/bxt_dsi.txt
@@ -0,0 +1,119 @@
+# NOTE: many of these are problematic, hard hanging the machine when they're
+# read without proper power domain or dsi pll enable.
+
+('MIPI_CLOCK_CTL', '0x46090', '')
+('MIPI_DSI_PLL_CTL', '0x161000', '')
+('MIPI_DSI_PLL_ENABLE, '0x46080', '')
+
+('MIPIA_TRANS_HACTIVE', '0x6B0F8', '')
+('MIPIA_TRANS_VACTIVE', '0x6B0FC', '')
+('MIPIA_TRANS_VTOTAL', '0x6B100', '')
+('MIPIA_PORT_CTRL', '0x6B0C0', '')
+('MIPIA_DEVICE_READY', '0x6B000', '')
+('MIPIA_INTR_STAT', '0x6B004', '')
+('MIPIA_INTR_EN', '0x6B008', '')
+('MIPIA_DSI_FUNC_PRG', '0x6B00C', '')
+('MIPIA_HS_TX_TIMEOUT', '0x6B010', '')
+('MIPIA_LP_RX_TIMEOUT', '0x6B014', '')
+('MIPIA_TURN_AROUND_TIMEOUT', '0x6B018', '')
+('MIPIA_DEVICE_RESET_TIMER', '0x6B01C', '')
+('MIPIA_DPI_RESOLUTION', '0x6B020', '')
+('MIPIA_DBI_FIFO_THROTTLE', '0x6B024', '')
+('MIPIA_HSYNC_PADDING_COUNT', '0x6B028', '')
+('MIPIA_HBP_COUNT', '0x6B02C', '')
+('MIPIA_HFP_COUNT', '0x6B030', '')
+('MIPIA_HACTIVE_AREA_COUNT', '0x6B034', '')
+('MIPIA_VSYNC_PADDING_COUNT', '0x6B038', '')
+('MIPIA_VBP_COUNT', '0x6B03C', '')
+('MIPIA_VFP_COUNT', '0x6B040', '')
+('MIPIA_HIGH_LOW_SWITCH_COUNT', '0x6B044', '')
+('MIPIA_DPI_CONTROL', '0x6B048', '')
+('MIPIA_DPI_DATA', '0x6B04C', '')
+('MIPIA_INIT_COUNT', '0x6B050', '')
+('MIPIA_MAX_RETURN_PKT_SIZE', '0x6B054', '')
+('MIPIA_VIDEO_MODE_FORMAT', '0x6B058', '')
+('MIPIA_EOT_DISABLE', '0x6B05C', '')
+('MIPIA_LP_BYTECLK', '0x6B060', '')
+('MIPIA_LP_GEN_DATA', '0x6B064', '')
+('MIPIA_HS_GEN_DATA', '0x6B068', '')
+('MIPIA_LP_GEN_CTRL', '0x6B06C', '')
+('MIPIA_HS_GEN_CTRL', '0x6B070', '')
+('MIPIA_GEN_FIFO_STAT', '0x6B074', '')
+('MIPIA_HS_LS_DBI_ENABLE', '0x6B078', '')
+('MIPIA_DPHY_PARAM', '0x6B080', '')
+('MIPIA_DBI_BW_CTRL', '0x6B084', '')
+('MIPIA_CLK_LANE_SWITCH_TIME_CNT', '0x6B088', '')
+('MIPIA_STOP_STATE_STALL', '0x6B08C', '')
+('MIPIA_INTR_STAT_REG_1', '0x6B090', '')
+('MIPIA_INTR_EN_REG_1', '0x6B094', '')
+('MIPIA_DBI_TYPEC_CTRL', '0x6B100', '')
+('MIPIA_CTRL', '0x6B104', '')
+('MIPIA_DATA_ADDRESS', '0x6B108', '')
+('MIPIA_DATA_LENGTH', '0x6B10C', '')
+('MIPIA_COMMAND_ADDRESS', '0x6B110', '')
+('MIPIA_COMMAND_LENGTH', '0x6B114', '')
+('MIPIA_READ_DATA_RETURN0', '0x6B118', '')
+('MIPIA_READ_DATA_RETURN1', '0x6B11C', '')
+('MIPIA_READ_DATA_RETURN2', '0x6B120', '')
+('MIPIA_READ_DATA_RETURN3', '0x6B124', '')
+('MIPIA_READ_DATA_RETURN4', '0x6B128', '')
+('MIPIA_READ_DATA_RETURN5', '0x6B12C', '')
+('MIPIA_READ_DATA_RETURN6', '0x6B130', '')
+('MIPIA_READ_DATA_RETURN7', '0x6B134', '')
+('MIPIA_READ_DATA_VALID', '0x6B138', '')
+
+('MIPIC_TRANS_HACTIVE', '0x6B8F8', '')
+('MIPIC_TRANS_VACTIVE', '0x6B8FC', '')
+('MIPIC_TRANS_VTOTAL', '0x6B900', '')
+('MIPIC_PORT_CTRL', '0x6B8C0', '')
+('MIPIC_DEVICE_READY', '0x6B800', '')
+('MIPIC_INTR_STAT', '0x6B804', '')
+('MIPIC_INTR_EN', '0x6B808', '')
+('MIPIC_DSI_FUNC_PRG', '0x6B80C', '')
+('MIPIC_HS_TX_TIMEOUT', '0x6B810', '')
+('MIPIC_LP_RX_TIMEOUT', '0x6B814', '')
+('MIPIC_TURN_AROUND_TIMEOUT', '0x6B818', '')
+('MIPIC_DEVICE_RESET_TIMER', '0x6B81C', '')
+('MIPIC_DPI_RESOLUTION', '0x6B820', '')
+('MIPIC_DBI_FIFO_THROTTLE', '0x6B824', '')
+('MIPIC_HSYNC_PADDING_COUNT', '0x6B828', '')
+('MIPIC_HBP_COUNT', '0x6B82C', '')
+('MIPIC_HFP_COUNT', '0x6B830', '')
+('MIPIC_HACTIVE_AREA_COUNT', '0x6B834', '')
+('MIPIC_VSYNC_PADDING_COUNT', '0x6B838', '')
+('MIPIC_VBP_COUNT', '0x6B83C', '')
+('MIPIC_VFP_COUNT', '0x6B840', '')
+('MIPIC_HIGH_LOW_SWITCH_COUNT', '0x6B844', '')
+('MIPIC_DPI_CONTROL', '0x6B848', '')
+('MIPIC_DPI_DATA', '0x6B84C', '')
+('MIPIC_INIT_COUNT', '0x6B850', '')
+('MIPIC_MAX_RETURN_PKT_SIZE', '0x6B854', '')
+('MIPIC_VIDEO_MODE_FORMAT', '0x6B858', '')
+('MIPIC_EOT_DISABLE', '0x6B85C', '')
+('MIPIC_LP_BYTECLK', '0x6B860', '')
+('MIPIC_LP_GEN_DATA', '0x6B864', '')
+('MIPIC_HS_GEN_DATA', '0x6B868', '')
+('MIPIC_LP_GEN_CTRL', '0x6B86C', '')
+('MIPIC_HS_GEN_CTRL', '0x6B870', '')
+('MIPIC_GEN_FIFO_STAT', '0x6B874', '')
+('MIPIC_HS_LS_DBI_ENABLE', '0x6B878', '')
+('MIPIC_DPHY_PARAM', '0x6B880', '')
+('MIPIC_DBI_BW_CTRL', '0x6B884', '')
+('MIPIC_CLK_LANE_SWITCH_TIME_CNT', '0x6B888', '')
+('MIPIC_STOP_STATE_STALL', '0x6B88C', '')
+('MIPIC_INTR_STAT_REG_1', '0x6B890', '')
+('MIPIC_INTR_EN_REG_1', '0x6B894', '')
+('MIPIC_CTRL', '0x6B904', '')
+('MIPIC_DATA_ADDRESS', '0x6B908', '')
+('MIPIC_DATA_LENGTH', '0x6B90C', '')
+('MIPIC_COMMAND_ADDRESS', '0x6B910', '')
+('MIPIC_COMMAND_LENGTH', '0x6B914', '')
+('MIPIC_READ_DATA_RETURN0', '0x6B918', '')
+('MIPIC_READ_DATA_RETURN1', '0x6B91C', '')
+('MIPIC_READ_DATA_RETURN2', '0x6B920', '')
+('MIPIC_READ_DATA_RETURN3', '0x6B924', '')
+('MIPIC_READ_DATA_RETURN4', '0x6B928', '')
+('MIPIC_READ_DATA_RETURN5', '0x6B92C', '')
+('MIPIC_READ_DATA_RETURN6', '0x6B930', '')
+('MIPIC_READ_DATA_RETURN7', '0x6B934', '')
+('MIPIC_READ_DATA_VALID', '0x6B938', '')
--
2.1.4
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