[Intel-gfx] [PATCH igt 16/17] intel_chipset: Replace lookup of GT size with computation

Chris Wilson chris at chris-wilson.co.uk
Wed Jun 29 11:39:06 UTC 2016 

Instead of a large if-chain for matching devid to GT, we can just
compute it directly from the encoded devid.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 debugger/eudb.c           |  14 +++---
 lib/intel_chipset.h       | 109 +---------------------------------------------
 lib/intel_device_info.c   |  23 ++++++++++
 tools/intel_l3_parity.c   |  15 +++----
 tools/intel_reg_checker.c |  19 ++++----
 5 files changed, 46 insertions(+), 134 deletions(-)

diff --git a/debugger/eudb.c b/debugger/eudb.c
index 47d5d92..866d4b5 100644
--- a/debugger/eudb.c
+++ b/debugger/eudb.c
@@ -351,16 +351,14 @@ die(int reason) {
 
 static int
 identify_device(int devid) {
-	switch(devid) {
-	case PCI_CHIP_SANDYBRIDGE_GT1:
-	case PCI_CHIP_SANDYBRIDGE_M_GT1:
-	case PCI_CHIP_SANDYBRIDGE_S:
+	if (!IS_SANDYBRIDGE(devid))
+		return -ENODEV;
+
+	switch (intel_gt(devid)) {
+	case 0:
 		eu_info = &gt1;
 		break;
-	case PCI_CHIP_SANDYBRIDGE_GT2:
-	case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
-	case PCI_CHIP_SANDYBRIDGE_M_GT2:
-	case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
+	case 1:
 		eu_info = &gt2;
 		break;
 	default:
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index e3e97ff..4234361 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -67,6 +67,7 @@ const struct intel_device_info {
 } *intel_device_info(uint16_t devid) __attribute__((pure));
 
 unsigned intel_gen(uint16_t devid) __attribute__((pure));
+unsigned intel_gt(uint16_t devid) __attribute__((pure));
 
 extern enum pch_type intel_pch;
 
@@ -269,114 +270,6 @@ void intel_check_pch(void);
 
 #endif /* __GTK_DOC_IGNORE__ */
 
-#define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
-#define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
-#define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
-				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
-
-#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
-
-#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
-
-#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
-
-#define IS_SKL_GT4(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT4	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT4	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4)
-
-#define IS_KBL_GT1(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5|| \
-				 (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT1|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1|| \
-				 (devid) == PCI_CHIP_KABYLAKE_DT_GT1||	\
-				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0|| \
-				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1|| \
-				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
-
-#define IS_KBL_GT2(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT2|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2|| \
-				 (devid) == PCI_CHIP_KABYLAKE_DT_GT2||	\
-				 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2|| \
-				 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2|| \
-				 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
-
-#define IS_KBL_GT3(devid)	((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1|| \
-				 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
-
-#define IS_KBL_GT4(devid)	((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
-
 #define IS_915G(devid)		(intel_device_info(devid)->is_grantsdale)
 #define IS_915GM(devid)		(intel_device_info(devid)->is_alviso)
 
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 7e26406..419f9f6 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -286,3 +286,26 @@ unsigned intel_gen(uint16_t devid)
 {
 	return ffs(intel_device_info(devid)->gen);
 }
+
+/**
+ * intel_gt:
+ * @devid: pci device id
+ *
+ * Computes the Intel GFX GT size for the given device id.
+ *
+ * Returns:
+ * The GT size.
+ */
+unsigned intel_gt(uint16_t devid)
+{
+	unsigned mask = intel_gen(devid);
+
+	if (mask >= 8)
+		mask = 0xf;
+	else if (mask >= 6)
+		mask = 0x3;
+	else
+		mask = 0;
+
+	return (devid >> 4) & mask;
+}
diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c
index 4810f7a..ecc0c61 100644
--- a/tools/intel_l3_parity.c
+++ b/tools/intel_l3_parity.c
@@ -51,14 +51,11 @@ static unsigned int devid;
 /* L3 size is always a function of banks. The number of banks cannot be
  * determined by number of slices however */
 static inline int num_banks(void) {
-	if (IS_HSW_GT3(devid))
-		return 8; /* 4 per each slice */
-	else if (IS_HSW_GT1(devid) ||
-			devid == PCI_CHIP_IVYBRIDGE_GT1 ||
-			devid == PCI_CHIP_IVYBRIDGE_M_GT1)
-		return 2;
-	else
-		return 4;
+	switch (intel_gt(devid)) {
+	case 2: return 8;
+	case 1: return 4;
+	default: return 2;
+	}
 }
 #define NUM_SUBBANKS 8
 #define BYTES_PER_BANK (128 << 10)
@@ -68,7 +65,7 @@ static inline int num_banks(void) {
 #define MAX_ROW (1<<12)
 #define MAX_BANKS_PER_SLICE 4
 #define NUM_REGS (MAX_BANKS_PER_SLICE * NUM_SUBBANKS)
-#define MAX_SLICES (IS_HSW_GT3(devid) ? 2 : 1)
+#define MAX_SLICES (intel_gt(devid) > 1 ? 2 : 1)
 #define REAL_MAX_SLICES 2
 /* TODO support SLM config */
 #define L3_SIZE ((MAX_ROW * 4) * NUM_SUBBANKS *  num_banks())
diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c
index 2d6da70..6bde63e 100644
--- a/tools/intel_reg_checker.c
+++ b/tools/intel_reg_checker.c
@@ -162,16 +162,17 @@ check_gt_mode(void)
 	if (gen == 6)
 		check_perf_bit(gt_mode, 8, "Full Rate Sampler Disable", false);
 
-	/* For DevSmallGT, this bit must be set, which means disable
-	 * hashing.
-	 */
-	if (devid == PCI_CHIP_SANDYBRIDGE_GT1 ||
-	    devid == PCI_CHIP_SANDYBRIDGE_M_GT1)
-		check_bit(gt_mode, 6, "WIZ Hashing disable", true);
-	else if (gen == 6)
-		check_perf_bit(gt_mode, 6, "WIZ Hashing disable", false);
-
 	if (gen == 6) {
+		/* For DevSmallGT, this bit must be set, which means disable
+		 * hashing.
+		 */
+		if (intel_gt(devid) == 0)
+			check_bit(gt_mode, 6,
+				  "WIZ Hashing disable", true);
+		else
+			check_perf_bit(gt_mode, 6,
+				       "WIZ Hashing disable", false);
+
 		check_perf_bit(gt_mode, 5, "TD Four Row Dispatch Disable",
 			       false);
 		check_perf_bit(gt_mode, 4, "Full Size URB Disable", false);
-- 
2.8.1

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