[Intel-gfx] [PATCH i-g-t v2] tests/pm_rpm: Fix CRASH on machines that lack LLC

[Chris Wilson]

On Wed, Mar 02, 2016 at 05:50:28PM +0200, David Weinehall wrote:
> On machines that lack an LLC the pm-caching subtest will
> terminate with sigbus and thus CRASH during the
> I915_CACHING_CACHED iteration.  This patch adds a check for
> this and uses I915_CACHING_NONE instead.
> 
> v2: Various improvements based on feedback from Chris Wilson
> 
> Signed-off-by: David Weinehall at linux.intel.com
> ---
>  tests/pm_rpm.c | 33 +++++++++++----------------------
>  1 file changed, 11 insertions(+), 22 deletions(-)
> 
> diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> index 2aa6c1018aa2..add8e2eb457f 100644
> --- a/tests/pm_rpm.c
> +++ b/tests/pm_rpm.c
> @@ -1800,7 +1800,7 @@ static void pm_test_caching(void)
>  	uint32_t handle;
>  	uint8_t *gem_buf;
>  
> -	uint32_t i, got_caching;
> +	uint32_t i;
>  	uint32_t gtt_obj_max_size = (16 * 1024);
>  	uint32_t cache_levels[3] = {
>  		I915_CACHING_NONE,
> @@ -1808,42 +1808,31 @@ static void pm_test_caching(void)
>  		I915_CACHING_DISPLAY,           /* eDRAM caching */
>  	};
>  
> +	disable_all_screens(&ms_data);
>  
>  	handle = gem_create(drm_fd, gtt_obj_max_size);
>  	gem_buf = gem_mmap__gtt(drm_fd, handle, gtt_obj_max_size, PROT_WRITE);
>  
>  	for (i = 0; i < ARRAY_SIZE(cache_levels); i++) {
> -		memset(gem_buf, 16 << i, gtt_obj_max_size);
> +		igt_assert(wait_for_suspended());
>  
> -		disable_all_screens_and_wait(&ms_data);
> +		memset(gem_buf, 16 << i, gtt_obj_max_size);
>  
>  		igt_debug("Setting cache level %u\n", cache_levels[i]);
>  
> -		gem_set_caching(drm_fd, handle, cache_levels[i]);
> -
> -		got_caching = gem_get_caching(drm_fd, handle);
> -
> -		igt_debug("Got back %u\n", got_caching);
> -
> -		/*
> -		 * Allow fall-back to CACHING_NONE in case the platform does
> -		 * not support it.
> -		 */
> -		if (cache_levels[i] == I915_CACHING_DISPLAY)
> -			igt_assert(got_caching == I915_CACHING_NONE ||
> -				   got_caching == I915_CACHING_DISPLAY);
> -		else
> -			igt_assert(got_caching == cache_levels[i]);
> -
> -		enable_one_screen_and_wait(&ms_data);
> +		/* If we lack an LLC cache we use I915_CACHING_NONE instead */
> +		if (cache_levels[i] == I915_CACHING_CACHED &&
> +		    !gem_has_llc(drm_fd)) {
> +			igt_debug("!gem_has_llc(); using I915_CACHING_NONE\n");
> +			gem_set_caching(drm_fd, handle, I915_CACHING_NONE);
> +		} else
> +			gem_set_caching(drm_fd, handle, cache_levels[i]);
>  	}
>  
>  	igt_assert(munmap(gem_buf, gtt_obj_max_size) == 0);
>  	gem_close(drm_fd, handle);
>  }

My argument is that:
unsigned default_level;

disable_all_screens(&ms_data);

handle = gem_create();
default_level = gem_get_caching();
ptr = gem_mmap__gtt()

for_each_level() {
	igt_assert(wait_for_suspended());
	gem_set_caching(default_level);

	/* Ensure we bind the vma into the GGTT */
	memset(ptr, 0, OBJECT_SIZE);

	/* Now try changing the cache-level on the bound object.
	 * This will either unlikely unbind the object from the GGTT,
	 * or more likely just change the PTEs inside the GGTT. Either
	 * way the driver must take the rpm wakelock around the GSM
	 * access.
	 */

	igt_assert(wait_for_suspended());
	gem_set_caching(this_level);

	//igt_assert_eq(intel_detect_and_clear_invalid_rpm_access(), 0);
}

is clearer to follow.

We should also add partial-vma exercising. For that, change OBJECT_SIZE
to be greater than the mappable aperture.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre