[Intel-gfx] [PATCH 0/5] Haswell Command Parser updates for Vulkan

Jordan Justen jordan.l.justen at intel.com
Mon Mar 7 07:30:25 UTC 2016

We need to whitelist some more registers for the Intel Haswell Vulkan
driver in Mesa. We need the TIMESTAMP counter and the CS GPR registers

The CS GPR registers are only present on Haswell, so I added the
ability to have an array of register tables. This allows all gen7
platforms to have a common set of render registers that are
whitelisted, while also allowing Haswell to have a separate set of
registers whitelisted. As part of this series, I moved the
HSW_SCRATCH1 and HSW_ROW_CHICKEN3 to only be whitelisted on Haswell.

I did not see any regressions in (OpenGL) piglit on Haswell with these
changes. I also confirmed that the newly whitelisted registers can now
be used by our Vulkan driver which shows that the separate table
appears to be functioning properly.

Jordan Justen (5):
  drm/i915: Add TIMESTAMP to register whitelist
  drm/i915: Use an array of register tables in command parser
  drm/i915: Move Haswell registers to separate whitelist table
  drm/i915: Add Haswell CS GPR registers to whitelist
  drm/i915: Bump command parser version for new whitelisted registers

 drivers/gpu/drm/i915/i915_cmd_parser.c  | 125 ++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/i915_reg.h         |   4 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |  13 +---
 3 files changed, 102 insertions(+), 40 deletions(-)


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