[Intel-gfx] [PATCH 8/8] drm/i915/skl: WA for watermark calculation based on Arbitrated Display BW (v4)
Matt Roper
matthew.d.roper at intel.com
Tue Mar 8 01:05:46 UTC 2016
From: "Kumar, Mahesh" <mahesh1.kumar at intel.com>
If the arbitary display bandwidth is > 60% of memory bandwith, for
x-tile we should increase latency at all levels by 15us.
If the arbitary dsplay bandwidth is greater than 20% of memory bandwith
in case of y-tile being enabled, double the scan lines
v2: Update the commit message to explain the WA (shobhit)
v3: - Address Damien's comment, use DIV_ROUND_UP_ULL macro
- Check both mem_speed and mem_channel to be valid before applying
WA(shobhit)
v4 (by Matt):
- Adjust calculations now that skl_plane_downscale_amount() returns
a 16.16 fixed point value
- Use pstate->visible instead of pstate->fb != NULL for determining
whether a plane is active
Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
Signed-off-by: Kumar, Mahesh <mahesh1.kumar at intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 9 ++++
drivers/gpu/drm/i915/intel_pm.c | 97 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 106 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2a7d8d..63b621a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1669,6 +1669,12 @@ enum intel_pipe_crc_source {
INTEL_PIPE_CRC_SOURCE_MAX,
};
+enum watermark_memory_wa {
+ WATERMARK_WA_NONE,
+ WATERMARK_WA_X_TILED,
+ WATERMARK_WA_Y_TILED,
+};
+
struct intel_pipe_crc_entry {
uint32_t frame;
uint32_t crc[5];
@@ -1973,6 +1979,9 @@ struct drm_i915_private {
/* Committed wm config */
struct intel_wm_config config;
+ /* This stores if WaterMark memory workaround is needed */
+ enum watermark_memory_wa mem_wa;
+
/*
* The skl_wm_values structure is a bit too big for stack
* allocation, so we keep the staging struct where we store
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 29d37d3..c1700af 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3286,6 +3286,11 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
return false;
+ if (dev_priv->wm.mem_wa != WATERMARK_WA_NONE) {
+ if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
+ latency += 15;
+ }
+
width = drm_rect_width(&intel_pstate->src) >> 16;
height = drm_rect_height(&intel_pstate->src) >> 16;
@@ -3325,6 +3330,9 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
WARN(1, "Unsupported pixel depth for rotation");
}
}
+ if (dev_priv->wm.mem_wa == WATERMARK_WA_Y_TILED)
+ min_scanlines *= 2;
+
y_tile_minimum = plane_blocks_per_line * min_scanlines;
selected_result = max(method2, y_tile_minimum);
} else {
@@ -3776,6 +3784,94 @@ static void skl_set_plane_pixel_rate(struct drm_crtc *crtc)
}
+static void
+skl_set_display_memory_wa(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = NULL;
+ struct intel_plane *intel_plane = NULL;
+ uint32_t num_active_crtc = 0;
+ uint64_t max_pixel_rate_pipe = 0;
+ uint64_t display_bw = 0, available_bw = 0;
+ bool y_tile_enabled = false;
+ int memory_portion = 0;
+
+ /* Verify that we got proper memory information */
+ if (!dev_priv->dmi.valid) {
+ dev_priv->wm.mem_wa = WATERMARK_WA_NONE;
+ return;
+ }
+
+ for_each_intel_crtc(dev, intel_crtc) {
+ uint64_t max_pixel_rate_plane = 0;
+ uint64_t pipe_bw;
+ uint32_t num_active_plane = 0;
+ const struct intel_crtc_state *cstate = NULL;
+
+ if (!intel_crtc->active)
+ continue;
+
+ cstate = to_intel_crtc_state(intel_crtc->base.state);
+ num_active_crtc++;
+
+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+ struct drm_plane *plane = &intel_plane->base;
+ struct drm_framebuffer *fb = plane->state->fb;
+ struct intel_plane_state *intel_pstate =
+ to_intel_plane_state(plane->state);
+ uint64_t plane_bw, interm_bw;
+
+ if (!intel_pstate->visible)
+ continue;
+ if (plane->type == DRM_PLANE_TYPE_CURSOR)
+ continue;
+
+ num_active_plane++;
+
+ if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED)
+ y_tile_enabled = true;
+
+ /*
+ * planeBW = pixel_rate(MHz) * BPP * plane downscale
+ * amount * pipe downscale amount;
+ *
+ * skl_pipe_pixel_rate returns the adjusted value
+ * according to the downscaling amount
+ *
+ * pixel rate is in KHz so divide it by 1000
+ *
+ * downscale factor is in 16.16 fixed point so shift
+ * the result accordingly
+ */
+ interm_bw = skl_pipe_pixel_rate(cstate)/1000 *
+ drm_format_plane_cpp(fb->pixel_format, 0) *
+ skl_plane_downscale_amount(intel_plane);
+
+ if (fb->pixel_format == DRM_FORMAT_NV12)
+ interm_bw += skl_pipe_pixel_rate(cstate)/1000 *
+ drm_format_plane_cpp(fb->pixel_format, 1) *
+ skl_plane_downscale_amount(intel_plane);
+
+ plane_bw = interm_bw >> 16;
+ max_pixel_rate_plane = max(max_pixel_rate_plane,
+ plane_bw);
+ }
+ pipe_bw = max_pixel_rate_plane * num_active_plane;
+ max_pixel_rate_pipe = max(max_pixel_rate_pipe, pipe_bw);
+ }
+
+ display_bw = max_pixel_rate_pipe * num_active_crtc;
+ available_bw = dev_priv->dmi.mem_channel * dev_priv->dmi.mem_speed * 8;
+ memory_portion = DIV_ROUND_UP_ULL((display_bw * 100), available_bw);
+
+ if (y_tile_enabled && (memory_portion >= 20))
+ dev_priv->wm.mem_wa = WATERMARK_WA_Y_TILED;
+ else if (memory_portion >= 60)
+ dev_priv->wm.mem_wa = WATERMARK_WA_X_TILED;
+ else
+ dev_priv->wm.mem_wa = WATERMARK_WA_NONE;
+}
+
static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
{
watermarks->wm_linetime[pipe] = 0;
@@ -3814,6 +3910,7 @@ static void skl_update_wm(struct drm_crtc *crtc)
/* Calculate plane pixel rate for each plane in advance */
skl_set_plane_pixel_rate(crtc);
+ skl_set_display_memory_wa(dev);
if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
goto out;
--
2.1.4
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