[Intel-gfx] [PATCH 4/5] drm/i915: Add Haswell CS GPR registers to whitelist

[Francisco Jerez]

Jordan Justen <jordan.l.justen at intel.com> writes:

> This is needed for the Mesa Vulkan driver on Haswell.
>
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>

Reviewed-by: Francisco Jerez <currojerez at riseup.net>

> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h        |  4 ++++
>  2 files changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index ba01836..e1608da 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -475,6 +475,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
>  };
>  
>  static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
> +	REG64_IDX(HSW_CS_GPR, 0),
> +	REG64_IDX(HSW_CS_GPR, 1),
> +	REG64_IDX(HSW_CS_GPR, 2),
> +	REG64_IDX(HSW_CS_GPR, 3),
> +	REG64_IDX(HSW_CS_GPR, 4),
> +	REG64_IDX(HSW_CS_GPR, 5),
> +	REG64_IDX(HSW_CS_GPR, 6),
> +	REG64_IDX(HSW_CS_GPR, 7),
> +	REG64_IDX(HSW_CS_GPR, 8),
> +	REG64_IDX(HSW_CS_GPR, 9),
> +	REG64_IDX(HSW_CS_GPR, 10),
> +	REG64_IDX(HSW_CS_GPR, 11),
> +	REG64_IDX(HSW_CS_GPR, 12),
> +	REG64_IDX(HSW_CS_GPR, 13),
> +	REG64_IDX(HSW_CS_GPR, 14),
> +	REG64_IDX(HSW_CS_GPR, 15),
>  	REG32(HSW_SCRATCH1,
>  	      .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
>  	      .value = 0),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f76cbf3..5ba7761 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -586,6 +586,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)
>  #define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)
>  
> +/* There are the 16 64-bit CS General Purpose Registers */
> +#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)
> +#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)
> +
>  #define OACONTROL _MMIO(0x2360)
>  
>  #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
> -- 
> 2.7.0
>
> _______________________________________________
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