[Intel-gfx] [RFCv3 12/15] drm/i915: Support context single submission

[Wang, Zhi A]

Hi Chris:
    We found that some guest would configure the render MMIOs via MMIO write, not like i915 which issues a lot of LRIs and configure the render mmio by itself(If they initialize their context like what i915 does, that would be nice..). 

Here is the scenario, guest configures render MMIOs via MMIO writes(GVT-g will store these values into virtual registers, as HW might be being used by someone else) and then guest submits a restore-inhibit LRC context. It assume currently the render MMIOs have been configured as what it wishes and these MMIO values should be saved into the context...

So  we have to reload the render MMIOs to HW for them before the context is submitted to HW by i915 GEM submission...

-----Original Message-----
From: Chris Wilson [mailto:chris at chris-wilson.co.uk] 
Sent: Friday, March 11, 2016 7:26 PM
To: Wang, Zhi A
Cc: intel-gfx at lists.freedesktop.org; igvt-g at lists.01.org; Tian, Kevin; Lv, Zhiyuan; Niu, Bing; Song, Jike; daniel.vetter at ffwll.ch; Cowperthwaite, David J; joonas.lahtinen at linux.intel.com
Subject: Re: [RFCv3 12/15] drm/i915: Support context single submission

On Fri, Mar 11, 2016 at 06:59:43PM +0800, Zhi Wang wrote:
> This patch introduces the support of context signle submission. As GVT
> context may come from different guests, which requires different
> configuration of render registers. It can't be combined in a dual ELSP
> submission combo.

That sounds wrong since the register are part of the context. I presume
what you mean is that you cannot combine requests from the same GVT
context but different guests.

> We make this function as a context feature in context creation service.
> Only GVT-g will create this kinds of GEM context currently.
> 
> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_lrc.c | 10 +++++++++-
>  drivers/gpu/drm/i915/intel_lrc.h |  1 +
>  3 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 68b821a..d7fc738 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -895,6 +895,7 @@ struct intel_context {
>  		bool need_status_change_notification;
>  		struct atomic_notifier_head status_notifier_head;
>  	} engine[I915_NUM_RINGS];
> +	bool single_submission;
>  
>  	struct list_head link;
>  };
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index ae1ab92..3a047fe 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -472,6 +472,9 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
>  				 execlist_link) {
>  		if (!req0) {
>  			req0 = cursor;
> +			/* req0 ctx requires single submission, stop picking */
> +			if (req0->ctx->single_submission)
> +				break;
>  		} else if (req0->ctx == cursor->ctx) {
>  			/* Same ctx: ignore first request, as second request
>  			 * will update tail past first request's workload */
> @@ -480,7 +483,12 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
>  				       &ring->execlist_retired_req_list);
>  			req0 = cursor;
>  		} else {
> -			req1 = cursor;
> +			/*
> +			 * req0 ctx doesn't require single submission, but
> +			 * next req ctx requires, stop picking req1
> +			 */
> +			if (!cursor->ctx->single_submission)
> +				req1 = cursor;
>  			break;
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 15791d4..4873dd8 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -107,6 +107,7 @@ struct intel_lr_context_alloc_params {
>  	u32 ringbuffer_size;
>  	bool ctx_needs_init;
>  	bool ctx_needs_status_change_notification;
> +	bool ctx_needs_single_submission;

Random garbage.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre