[Intel-gfx] [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout

[Jani Nikula]

On Tue, 15 Mar 2016, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Use the proper refclock frequency (100MHz) when reading out the
> current DSI clock on CHV.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index d35c8dc28fb6..99236baa946b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -255,7 +255,7 @@ static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
>  	u32 dsi_clock, pclk;
>  	u32 pll_ctl, pll_div;
>  	u32 m = 0, p = 0, n;
> -	int refclk = 25000;
> +	int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000;
>  	int i;
>  
>  	DRM_DEBUG_KMS("\n");

-- 
Jani Nikula, Intel Open Source Technology Center