[Intel-gfx] [PATCH v3] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave

[Arun Siluvery]

On 16/03/2016 16:13, tim.gore at intel.com wrote:
> From: Tim Gore <tim.gore at intel.com>
>
> This allows writes to EU flow control registers. Together
> with SIP code from the user-mode driver this resolves a
> hang seen in some pre-emption scenarios. Note that this
> patch is just the kernel mode part of this workaround.
>
> v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h.
>
> Signed-off-by: Tim Gore <tim.gore at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h         | 1 +
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
>   2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 85ceec6..adab0f0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7103,6 +7103,7 @@ enum skl_disp_power_wells {
>   #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1<<3)
>
>   #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
> +#define   FLOW_CONTROL_ENABLE		(1<<15)
>   #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1<<8)
>   #define   STALL_DOP_GATING_DISABLE		(1<<5)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 015dc7d..b6f6b3b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -925,8 +925,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>   	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>   		   ECOCHK_DIS_TLB);
>
> +	/* WaClearFlowControlGpgpuContextSave:skl,bxt */
>   	/* WaDisablePartialInstShootdown:skl,bxt */
>   	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> +			  FLOW_CONTROL_ENABLE |
>   			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>
>   	/* Syncing dependencies between camera and graphics:skl,bxt */
>
looks good to me,
Reviewed-by: Arun Siluvery <arun.siluvery at linux.intel.com>

regards
Arun