[Intel-gfx] [PATCH 11/15] drm/i915: Merge ironlake_compute_clocks() and ironlake_crtc_compute_clock()

[Ville Syrjälä]

On Mon, Mar 21, 2016 at 06:00:12PM +0200, Ander Conselvan de Oliveira wrote:
> Merge ironlake_compute_clocks() into ironlake_crtc_compute_clock() so
> the clock computation logic is all in one place. The resulting function
> is still quite simple. Follow up patches will make the similar code for
> GMCH platforms look similar.
> 
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 86 ++++++++++++++----------------------
>  1 file changed, 33 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b6541a0..13b509e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -848,6 +848,11 @@ pnv_find_best_dpll(const intel_limit_t *limit,
>  	return (err != target);
>  }
>  
> +/*
> + * Returns a set of divisors for the desired target clock with the given
> + * refclk, or FALSE.  The returned values represent the clock equation:
> + * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> + */
>  static bool
>  g4x_find_best_dpll(const intel_limit_t *limit,
>  		   struct intel_crtc_state *crtc_state,
> @@ -8756,55 +8761,6 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc)
>  	}
>  }
>  
> -static bool ironlake_compute_clocks(struct drm_crtc *crtc,
> -				    struct intel_crtc_state *crtc_state,
> -				    intel_clock_t *clock,
> -				    bool *has_reduced_clock,
> -				    intel_clock_t *reduced_clock)
> -{
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int refclk;
> -	const intel_limit_t *limit;
> -	bool ret;
> -
> -	refclk = 120000;
> -
> -	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> -		if (intel_panel_use_ssc(dev_priv)) {
> -			DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
> -				      dev_priv->vbt.lvds_ssc_freq);
> -			refclk = dev_priv->vbt.lvds_ssc_freq;
> -		}
> -
> -		if (intel_is_dual_link_lvds(dev)) {
> -			if (refclk == 100000)
> -				limit = &intel_limits_ironlake_dual_lvds_100m;
> -			else
> -				limit = &intel_limits_ironlake_dual_lvds;
> -		} else {
> -			if (refclk == 100000)
> -				limit = &intel_limits_ironlake_single_lvds_100m;
> -			else
> -				limit = &intel_limits_ironlake_single_lvds;
> -		}
> -	} else {
> -		limit = &intel_limits_ironlake_dac;
> -	}
> -
> -	/*
> -	 * Returns a set of divisors for the desired target clock with the given
> -	 * refclk, or FALSE.  The returned values represent the clock equation:
> -	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
> -	 */
> -	ret = g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> -				 refclk, NULL, clock);
> -	if (!ret)
> -		return false;
> -
> -	return true;
> -}
> -
>  int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
>  {
>  	/*
> @@ -8929,9 +8885,13 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
>  static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
>  				       struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  	intel_clock_t reduced_clock;
>  	bool has_reduced_clock = false;
>  	struct intel_shared_dpll *pll;
> +	const intel_limit_t *limit;
> +	int refclk = 120000;
>  
>  	memset(&crtc_state->dpll_hw_state, 0,
>  	       sizeof(crtc_state->dpll_hw_state));
> @@ -8942,11 +8902,31 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
>  	if (!crtc_state->has_pch_encoder)
>  		return 0;
>  
> +	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
> +		if (intel_panel_use_ssc(dev_priv)) {
> +			DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
> +				      dev_priv->vbt.lvds_ssc_freq);
> +			refclk = dev_priv->vbt.lvds_ssc_freq;
> +		}
> +
> +		if (intel_is_dual_link_lvds(dev)) {
> +			if (refclk == 100000)
> +				limit = &intel_limits_ironlake_dual_lvds_100m;
> +			else
> +				limit = &intel_limits_ironlake_dual_lvds;
> +		} else {
> +			if (refclk == 100000)
> +				limit = &intel_limits_ironlake_single_lvds_100m;
> +			else
> +				limit = &intel_limits_ironlake_single_lvds;
> +		}
> +	} else {
> +		limit = &intel_limits_ironlake_dac;
> +	}
> +
>  	if (!crtc_state->clock_set &&
> -	    !ironlake_compute_clocks(&crtc->base, crtc_state,
> -				     &crtc_state->dpll,
> -				     &has_reduced_clock,
> -				     &reduced_clock)) {
> +	    !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
> +				refclk, NULL, &crtc_state->dpll)) {
>  		DRM_ERROR("Couldn't find PLL settings for mode!\n");
>  		return -EINVAL;
>  	}
> -- 
> 2.4.3
> 
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-- 
Ville Syrjälä
Intel OTC